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Fuzzy matching: Hardware accelerated MPI communication middleware

Proceedings - 19th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing, CCGrid 2019

Dosanjh, Matthew G.; Schonbein, William W.; Grant, Ryan; Bridges, Patrick G.; Gazimirsaeed, S.M.; Afsahi, Ahmad

Contemporary parallel scientific codes often rely on message passing for inter-process communication. However, inefficient coding practices or multithreading (e.g., via MPI-THREAD-MULTIPLE) can severely stress the underlying message processing infrastructure, resulting in potentially un-acceptable impacts on application performance. In this article, we propose and evaluate a novel method for addressing this issue: 'Fuzzy Matching'. This approach has two components. First, it exploits the fact most server-class CPUs include vector operations to parallelize message matching. Second, based on a survey of point-to-point communication patterns in representative scientific applications, the method further increases parallelization by allowing matches based on 'partial truth', i.e., by identifying probable rather than exact matches. We evaluate the impact of this approach on memory usage and performance on Knight's Landing and Skylake processors. At scale (262,144 Intel Xeon Phi cores), the method shows up to 1.13 GiB of memory savings per node in the MPI library, and improvement in matching time of 95.9%; smaller-scale runs show run-time improvements of up to 31.0% for full applications, and up to 6.1% for optimized proxy applications.

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TYPE Conference Poster YEAR 2019
DOIOSTIScopus

Sub-10μm pitch hybrid direct bond interconnect development for die-to-die hybridization

Proceedings - Electronic Components and Technology Conference

Mudrick, John P.; Sierra Suarez, Jonatan; Jordan, Matthew; Friedmann, Thomas A.; Jarecki, Robert; Henry, Michael D.

Direct bond interconnect (DBI) processes enable chip to chip, low resistivity electrical connections for 2.5-D scaling of electrical circuits and heterogenous integration. This work describes SiO2/Cu DBI technology with Cu interconnect performance investigated over a range of inter-die Cu gap heights and post-bond annealing temperatures. Chemical mechanical polishing (CMP) generates wafers with a controlled Cu recess relative to the SiO2 surface, yielding die pairs with inter-die Cu gap heights ranging between 9 and 47 nm. Bonded die with different gap heights show similar per-connection resistance after annealing at 400 degrees Celsius but annealing at lower temperatures between 250 and 350 degrees Celsius results in failing or high-resistance interconnects with intermediate gaps showing lowest resistance. Cross-section scanning electron microscope (SEM) image analysis shows that the microstructure is largely independent of post-bond annealing temperature, suggesting that the temperature behavior is due to nanoscale scale interfacial effects not observable by SEM. The bond strength is affirmed by successful step-wise mechanical and chemical removal of the handle silicon layer to reveal metal from both die. This work demonstrates a 2.5-D integration method using a 3 micron Cu DBI process on a 7.5 micron pitch with electrical contacts ranging between 3.8 and 4.8 Ohms per contact plug.

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TYPE Conference Poster YEAR 2019
OSTIScopus
Results 23601–23800 of 99,299
Results 23601–23800 of 99,299