We report on the characterization of heating rates and photoinduced electric charging on a microfabricated surface ion trap with integrated waveguides. Microfabricated surface ion traps have received considerable attention as a quantum information platform due to their scalability and manufacturability. Here, we characterize the delivery of 435-nm light through waveguides and diffractive couplers to a single ytterbium ion in a compact trap. We measure an axial heating rate at room temperature of 0.78±0.05 q/ms and see no increase due to the presence of the waveguide. Furthermore, the electric field due to charging of the exposed dielectric outcoupler settles under normal operation after an initial shift. The frequency instability after settling is measured to be 0.9 kHz.
Surging interest in engineering quantum computers has stimulated significant and focused research on technologies needed to make them manufacturable and scalable. In the ion trap realm this has led to a transition from bulk three-dimensional macro-scale traps to chip-based ion traps and included important demonstrations of passive and active electronics, waveguides, detectors, and other integrated components. At the same time as these technologies are being developed the system sizes are demanding more ions to run noisy intermediate scale quantum (NISQ) algorithms, growing from around ten ions today to potentially a hundred or more in the near future. To realize the size and features needed for this growth, the geometric and material design space of microfabricated ion traps must expand. In this paper we describe present limitations and the approaches needed to overcome them, including how geometric complexity drives the number of metal levels, why routing congestion affects the size and location of shunting capacitors, and how RF power dissipation can limit the size of the trap array. We also give recommendations for future research needed to accommodate the demands of NISQ scale ion traps that are integrated with additional technologies.
Atomic clocks are precision timekeeping devices that form the basis for modern communication and navigation. While many atomic clocks are room-sized systems requiring bulky free space optics and detectors, the Trapped-lon Clock using Technology-On-Chip (TICTOC) project integrates these components into Sandia's existing surface trap technology via waveguides for beam delivery and avalanche photodiodes for light detection. Taking advantage of a multi-ensemble clock interrogation approach, we expect to achieve record time stability (< 1 ns error per year) in a compact (< /1 2 L) clock. Here, we present progress on the development of the integrated devices and recent trapped ion demonstrations.
This work demonstrates void-free Cu filling of millimeter size Through Silicon Vias (mm-TSV) in an acid copper sulfate electrolyte using a combination of a polyoxamine suppressor and chloride, analogous to previous work filling TSV that were an order of magnitude smaller in size. For high chloride concentration (i.e., 1 mmol/L) bottom-up deposition is demonstrated with the growth front being convex in shape. Instabilities in filling profile arise as the growth front approaches the freesurface due to non-uniform coupling with electrolyte hydrodynamics Filling is negatively impacted by large lithography-induced reentrant notches that increase the via cross section at the bottom. In contrast, deposition from low chloride electrolytes, proceeds with a passive-active transition on the via sidewalls. For a given applied potential the location of the transition is fixed in time and the growth front is concave in nature reflecting the gradient in chloride surface coverage. Application of a suitable potential wave form enables the location of the sidewall transition to be advanced thereby giving rise to void-free filling of the TSV.
An electrodeposition process for void-free bottom-up filling of sub-millimeter scale through silicon vias (TSVs) with Cu is detailed. The 600 μm deep and nominally 125 μm diameter metallized vias were filled with Cu in less than 7 hours under potentiostatic control. The electrolyte is comprised of 1.25 mol/L CuSO4 - 0.25 mol/L CH3SO3H with polyether and halide additions that selectively suppress metal deposition on the free surface and side walls. A brief qualitative discussion of the procedures used to identify and optimize the bottom-up void-free feature filling is presented.
A methanesulfonic acid (MSA) electrolyte with a single suppressor additive was used for potentiostatic bottom-up filling of copper in mesoscale through silicon vias (TSVs). Conversly, galvanostatic deposition is desirable for production level full wafer plating tools as they are typically not equipped with reference electrodes which are required for potentiostatic plating. Potentiostatic deposition was used to determine the over-potential required for bottom-up TSV filling and the resultant current was measured to establish a range of current densities to investigate for galvanostatic deposition. Galvanostatic plating conditions were then optimized to achieve void-free bottom-up filling in mesoscale TSVs for a range of sample sizes.