Five alternative metals are investigated as ohmic contacts to n-GaN including Cr/Au, Mo/Au, Pt/Au, Pd/Au, and Ge/Au. Ti-based contacts are traditionally used for ohmic contacts on n-GaN. However, conventional Ti/Al/Ni/Au metallization is found to be incompatible with a self-aligned process for GaN trench MOSFETs due to wet etch restrictions. Therefore, an alternative metallization is needed that is unreactive to the etch chemistry used in the self-aligned process. Additionally, the contact should remain ohmic following anneal at 900 °C so that contact formation can precede the anneal required for p-dopant activation. Here, in the present work, an n-GaN bilayer, consisting of a thin heavily doped contact layer (n0 = 1 × 1020 cm−3) atop a thick lesser doped layer, is used to demonstrate ohmic contacts of alternative metals with low specific contact resistance and extended thermal budget. Cr/Au ohmic contacts are demonstrated up to anneal temperatures of 800 °C, an increase of 200 °C compared to the highest known reports for Cr/Au contacts on n-GaN. Pt/Au metallization is demonstrated as an ohmic contact to n-GaN for the first time and exhibits true temperature-agnostic behavior up to anneal temperatures of 900 °C with specific contact resistance that is near parity with Ti/Al/Ni/Au. The temperature-agnostic behavior of Pt/Au ohmic contacts on the n-GaN bilayer, in addition to chemical compatibility with the self-aligned process, positions Pt/Au contacts as a key enabling element for self-aligned trench MOSFETs on GaN.
Characterizing interface trap states in commercial wide bandgap devices using frequency-based measurements requires unconventionally high probing frequencies to account for both fast and slow traps associated with wide bandgap materials. The C − ψ S technique has been suggested as a viable quasi-static method for determining the interface trap state densities in wide bandgap systems, but the results are shown to be susceptible to errors in the analysis procedure. This work explores the primary sources of errors present in the C − ψ S technique using an analytical model that describes the apparent response for wide bandgap MOS capacitor devices. Measurement noise is shown to greatly impact the linear fitting routine of the 1 / C S ∗ 2 vs ψ S plot to calibrate the additive constant in the surface potential/gate voltage relationship, and an inexact knowledge of the oxide capacitance is also shown to impede interface trap state analysis near the band edge. In addition, a slight nonlinearity that is typically present throughout the 1 / C S ∗ 2 vs ψ S plot hinders the accurate estimation of interface trap densities, which is demonstrated for a fabricated n-SiC MOS capacitor device. Methods are suggested to improve quasi-static analysis, including a novel method to determine an approximate integration constant without relying on a linear fitting routine.
This paper describes a process for forming a buried field shield in GaN by an etch-and-regrowth process, which is intended to protect the gate dielectric from high fields in the blocking state. GaN trench MOSFETs made at Sandia serve as the baseline to show the limitations in making a trench gated device without a method to protect the gate dielectric. Device data coupled with simulations show device failure at 30% of theoretical breakdown for devices made without a field shield. Implementation of a field shield reduces the simulated electric field in the dielectric to below 4 MV/cm at breakdown, which eliminates the requirement to derate the device in order to protect the dielectric. For realistic lithography tolerances, however, a shield-to-channel distance of 0.4 μm limits the field in the gate dielectric to 5 MV/cm and requires a small margin of device derating to safeguard a long-term reliability and lifetime of the dielectric.
Here we report on AlGaN high electron mobility transistor (HEMT)-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature-dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data (from 30°C to 500°C) revealed the reference GaN-channel HEMT experienced a 6.9x reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200-nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.
High reliability (Hi-Rel) electronics for mission critical applications are handled with extreme care; stress testing upon full assembly can increase a likelihood of degrading these systems before their deployment. Moreover, novel material parts, such as wide bandgap semiconductor devices, tend to have more complicated fabrication processing needs which could ultimately result in larger part variability or potential defects. Therefore, an intelligent screening and inspection technique for electronic parts, in particular gallium nitride (GaN) power transistors, is presented in this paper. We present a machine-learning-based non-intrusive technique that can enhance part-selection decisions to categorize the part samples to the population's expected electrical characteristics. This technique provides relevant information about GaN HEMT device characteristics without having to operate all of these devices at the high current region of the transfer and output characteristics, lowering the risk of damaging the parts prematurely. The proposed non-intrusive technique uses a small signal pulse width modulation (PWM) of various frequencies, ranging from 10 kHz to 500 kHz, injected into the transistor terminals and the corresponding output signals are observed and used as training dataset. Unsupervised clustering techniques with K-means and feature dimensional reduction through principal component analysis (PCA) have been used to correlate a population of GaN HEMT transistors to the expected mean of the devices' electrical characteristic performance.
