As quantum computing hardware becomes more complex with ongoing design innovations and growing capabilities, the quantum computing community needs increasingly powerful techniques for fabrication failure root-cause analysis. This is especially true for trapped-ion quantum computing. As trapped-ion quantum computing aims to scale to thousands of ions, the electrode numbers are growing to several hundred, with likely integrated photonic components also adding to the electrical and fabrication complexity, making faults even harder to locate. In this work, we used a high-resolution quantum magnetic imaging technique, based on nitrogen-vacancy centers in diamond, to investigate short-circuit faults in an ion trap chip. We imaged currents from these short-circuit faults to ground and compared them to intentionally created faults, finding that the root cause of the faults was failures in the on-chip trench capacitors. This work, where we exploited the performance advantages of a quantum magnetic sensing technique to troubleshoot a piece of quantum computing hardware, is a unique example of the evolving synergy between emerging quantum technologies to achieve capabilities that were previously inaccessible.
We demonstrate an order of magnitude reduction in the sensitivity to optical crosstalk for neighboring trapped-ion qubits during simultaneous single-qubit gates driven with individual addressing beams. Gates are implemented via two-photon Raman transitions, where crosstalk is mitigated by offsetting the drive frequencies for each qubit to avoid first-order crosstalk effects from inter-beam two-photon resonance. The technique is simple to implement, and we find that phase-dependent crosstalk due to optical interference is reduced on the most impacted neighbor from a maximal fractional rotation error of 0.185 ( 4 ) without crosstalk mitigation to ≤ 0.006 with the mitigation strategy. Furthermore, we characterize first-order crosstalk in the two-qubit gate and avoid the resulting rotation errors for the arbitrary-axis Mølmer-Sørensen gate via a phase-agnostic composite gate. Finally, we demonstrate holistic system performance by constructing a composite CNOT gate using the improved single-qubit gates and phase-agnostic two-qubit gate. This work is done on the Quantum Scientific Computing Open User Testbed; however, our methods are widely applicable for individual addressing Raman gates and impose no significant overhead, enabling immediate improvement for quantum processors that incorporate this technique.
The Roadrunner ion trap is a micro-fabricated surface-electrode ion trap based on silicon technology. This trap has one long linear section and a junction to allow for chain storage and reconfiguration. It uses a symmetric rf-rail design with segmented inner and outer control electrodes and independent control in the junction arms. The trap is fabricated on Sandia’s High Optical Access (HOA) platform to provide good optical access for tightly focused laser beams skimming the trap surface. It is packaged on our custom Bowtie-102 ceramic pin or land grid array packages using a 2.54 mm pitch for backside pins or pads. This trap also includes an rf sensing capacitive divider and tungsten wires for heating or temperature monitoring. The Roadrunner builds on the knowledge gained from previous surface traps fabricated at Sandia while improving ion control capabilities.
Most near-term quantum information processing devices will not be capable of implementing quantum error correction and the associated logical quantum gate set. Instead, quantum circuits will be implemented directly using the physical native gate set of the device. These native gates often have a parameterization (e.g., rotation angles) which provide the ability to perform a continuous range of operations. Verification of the correct operation of these gates across the allowable range of parameters is important for gaining confidence in the reliability of these devices. In this work, we demonstrate a procedure for sample-efficient verification of continuously-parameterized quantum gates for small quantum processors of up to approximately 10 qubits. This procedure involves generating random sequences of randomly-parameterized layers of gates chosen from the native gate set of the device, and then stochastically compiling an approximate inverse to this sequence such that executing the full sequence on the device should leave the system near its initial state. We show that fidelity estimates made via this technique have a lower variance than fidelity estimates made via cross-entropy benchmarking. This provides an experimentally-relevant advantage in sample efficiency when estimating the fidelity loss to some desired precision. We describe the experimental realization of this technique using continuously-parameterized quantum gate sets on a trapped-ion quantum processor from Sandia QSCOUT and a superconducting quantum processor from IBM Q, and we demonstrate the sample efficiency advantage of this technique both numerically and experimentally.
Quantum computing testbeds exhibit high-fidelity quantum control over small collections of qubits, enabling performance of precise, repeatable operations followed by measurements. Currently, these noisy intermediate-scale devices can support a sufficient number of sequential operations prior to decoherence such that near term algorithms can be performed with proximate accuracy (like chemical accuracy for quantum chemistry problems). While the results of these algorithms are imperfect, these imperfections can help bootstrap quantum computer testbed development. Demonstrations of these algorithms over the past few years, coupled with the idea that imperfect algorithm performance can be caused by several dominant noise sources in the quantum processor, which can be measured and calibrated during algorithm execution or in post-processing, has led to the use of noise mitigation to improve typical computational results. Conversely, benchmark algorithms coupled with noise mitigation can help diagnose the nature of the noise, whether systematic or purely random. Here, we outline the use of coherent noise mitigation techniques as a characterization tool in trapped-ion testbeds. We perform model-fitting of the noisy data to determine the noise source based on realistic physics focused noise models and demonstrate that systematic noise amplification coupled with error mitigation schemes provides useful data for noise model deduction. Further, in order to connect lower level noise model details with application specific performance of near term algorithms, we experimentally construct the loss landscape of a variational algorithm under various injected noise sources coupled with error mitigation techniques. This type of connection enables application-aware hardware code-sign, in which the most important noise sources in specific applications, like quantum chemistry, become foci of improvement in subsequent hardware generations.
Next generation ion traps will likely need to support tens if not hundreds of ions in order to achieve several logical qubits. As we scale to those sizes, the same problems we face now – rf dissipation, control I/O, and optical access – will only grow and become more complicated. While many of these challenges can potentially be solved with technology integration, independently researching the feasibility of that integration and other solutions may help reduce the time and risk in scaling up to larger traps, by testing on smaller less complex devices. We should also consider other fabrication techniques that may help scale to larger devices, such as: through-substrate-vias (TSVs), different metal coatings, exotic rf routing, on chip laser sources, or even a secondary macroscopic trap to reload ions from. To have these technologies ready for full scale integration when we need them, ion traps with some of these capabilities need to be produced now. Developing the rigorous fabrication methods for producing reliable traps takes time and experimentation. We propose developing larger ion traps and reliable integrated technology in conjunction to make both available faster.