The Roadrunner ion trap is a micro-fabricated surface-electrode ion trap based on silicon technology. This trap has one long linear section and a junction to allow for chain storage and reconfiguration. It uses a symmetric rf-rail design with segmented inner and outer control electrodes and independent control in the junction arms. The trap is fabricated on Sandia’s High Optical Access (HOA) platform to provide good optical access for tightly focused laser beams skimming the trap surface. It is packaged on our custom Bowtie-102 ceramic pin or land grid array packages using a 2.54 mm pitch for backside pins or pads. This trap also includes an rf sensing capacitive divider and tungsten wires for heating or temperature monitoring. The Roadrunner builds on the knowledge gained from previous surface traps fabricated at Sandia while improving ion control capabilities.
Here we report on AlGaN high electron mobility transistor (HEMT)-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature-dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data (from 30°C to 500°C) revealed the reference GaN-channel HEMT experienced a 6.9x reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200-nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.
We report on AlGaN HEMT-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data revealed the GaN-channel HEMT experienced a 6.9× reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200 nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.
This project developed prototype germanium telluride switches, which can be used in RF applications to improve SWAP (size, weight, and power) and signal quality in RF systems. These switches can allow for highly reconfigurable systems, including antennas, communications, optical systems, phased arrays, and synthetic aperture radar, which all have high impact on current National Security goals for improved communication systems and communication technology supremacy. The final result of the project was the demonstration of germanium telluride RF switches, which could act as critical elements necessary for a single chip RF communication system that will demonstrate low SWAP and high reconfigurability
Surging interest in engineering quantum computers has stimulated significant and focused research on technologies needed to make them manufacturable and scalable. In the ion trap realm this has led to a transition from bulk three-dimensional macro-scale traps to chip-based ion traps and included important demonstrations of passive and active electronics, waveguides, detectors, and other integrated components. At the same time as these technologies are being developed the system sizes are demanding more ions to run noisy intermediate scale quantum (NISQ) algorithms, growing from around ten ions today to potentially a hundred or more in the near future. To realize the size and features needed for this growth, the geometric and material design space of microfabricated ion traps must expand. In this paper we describe present limitations and the approaches needed to overcome them, including how geometric complexity drives the number of metal levels, why routing congestion affects the size and location of shunting capacitors, and how RF power dissipation can limit the size of the trap array. We also give recommendations for future research needed to accommodate the demands of NISQ scale ion traps that are integrated with additional technologies.
Plasmas formed in microscale gaps at DC and plasmas formed at radiofrequency (RF) both deviate in behavior compared to the classical Paschen curve, requiring lower voltage to achieve breakdown due to unique processes and dynamics, such as field emission and controlled rates of electron/ion interactions. Both regimes have been investigated independently, using high precision electrode positioning systems for microscale gaps or large, bulky emitters for RF. However, no comprehensive study of the synergistic phenomenon between the two exists. The behavior in such a combined system has the potential to reach sub-10 V breakdown, which combined with the unique electrical properties of microscale plasmas could enable a new class of RF switches, limiters and tuners.This work describes the design and fabrication of novel on-wafer microplasma devices with gaps as small as 100 nm to be operated at GHz frequencies. We used a dual-sacrificial layer process to create devices with microplasma gaps integrated into RF compatible 50 Ω coplanar waveguide transmission lines, which will allow this coupled behaviour to be studied for the first time. These devices are modelled using conventional RF simulations as well as the Sandia code, EMPIRE, which is capable of modelling the breakdown and formation of plasma in microscale gaps driven by high frequencies. Synchronous evaluation of the modelled electrical and breakdown behaviour is used to define device structures, predict behaviour and corroborate results. We further report preliminary independent testing of the microscale gap and RF behaviour. DC testing shows modified-Paschen curve behaviour for plasma gaps at and below four microns, demonstrating decreased breakdown voltage with reduced gap size. Additionally, preliminary S-parameter measurements of as-prepared and connectorized devices have elucidated RF device behaviour. Together, these results provide baseline data that enables future experiments as well as discussion of projected performance and applications for these unique devices.
We present an optical wavelength division multiplexer enabled by a ring resonator tuned by MEMS electrostatic actuation. Analytical analysis, simulation and fabrication are discussed leading to results showing controlled tuning greater than one FSR.
We present an optical wavelength division multiplexer enabled by a ring resonator tuned by MEMS electrostatic actuation. Analytical analysis, simulation and fabrication are discussed leading to results showing controlled tuning greater than one FSR.
Heterogeneous Integration (HI) may enable optoelectronic transceivers for short-range and long-range radio frequency (RF) photonic interconnect using wavelength-division multiplexing (WDM) to aggregate signals, provide galvanic isolation, and reduce crosstalk and interference. Integration of silicon Complementary Metal-Oxide-Semiconductor (CMOS) electronics with InGaAsP compound semiconductor photonics provides the potential for high-performance microsystems that combine complex electronic functions with optoelectronic capabilities from rich bandgap engineering opportunities, and intimate integration allows short interconnects for lower power and latency. The dominant pure-play foundry model plus the differences in materials and processes between these technologies dictate separate fabrication of the devices followed by integration of individual die, presenting unique challenges in die preparation, metallization, and bumping, especially as interconnect densities increase. In this paper, we describe progress towards realizing an S-band WDM RF photonic link combining 180 nm silicon CMOS electronics with InGaAsP integrated optoelectronics, using HI processes and approaches that scale into microwave and millimeter-wave frequencies.
The ultrawide bandgap (UWBG) (4.8 eV) and melt-grown substrate availability of β-Ga2O3 give promise to the development of next-generation power electronic devices with dramatically improved size, weight, power, and efficiency over current state-of-the-art WBG devices based on 4H-SiC and GaN. Also, with recent advancements made in gigahertz frequency radio frequency (RF) applications, the potential for monolithic or heterogenous integration of RF and power switches has attracted researchers' attention. However, it is expected that Ga2O3 devices will suffer from self-heating due to the poor thermal conductivity of the material. Thermoreflectance thermal imaging and infrared thermography were used to understand the thermal characteristics of a MOSFET fabricated via homoepitaxy. A 3-D coupled electrothermal model was constructed based on the electrical and thermal characterization results. The device model shows that a homoepitaxial device suffers from an unacceptable junction temperature rise of 1500 °C under a targeted power density of 10 W/mm, indicating the importance of employing device-level thermal managements to individual Ga2O3 transistors. The effectiveness of various active and passive cooling solutions was tested to achieve a goal of reducing the device operating temperature below 200 °C at a power density of 10 W/mm. Results show that flip-chip heterointegration is a viable option to enhance both the steady-state and transient thermal characteristics of Ga2O3 devices without sacrificing the intrinsic advantage of high-quality native substrates. Also, it is not an active thermal management solution that entails peripherals requiring additional size and cost implications.
Gate length dependent (80 nm–5000 mm) radio frequency measurements to extract saturation velocity are reported for Al0.85Ga0.15N/Al0.7Ga0.3N high electron mobility transistors fabricated into radio frequency devices using electron beam lithography. Direct current characterization revealed the threshold voltage shifting positively with increasing gate length, with devices changing from depletion mode to enhancement mode when the gate length was greater than or equal to 450 nm. Transconductance varied from 10 mS/mm to 25 mS/mm, with the 450 nm device having the highest values. Maximum drain current density was 268 mA/mm at 10 V gate bias. Scattering-parameter characterization revealed a maximum unity gain bandwidth (fT) of 28 GHz, achieved by the 80 nm gate length device. A saturation velocity value of 3.8 × 106 cm/s, or 35% of the maximum saturation velocity reported for GaN, was extracted from the fT measurements.
Al-rich AlGaN-channel high electron mobility transistors with 80-nm long gates and 85% (70%) Al in the barrier (channel) were evaluated for RF performance. The dc characteristics include a maximum current of 160 mA/mm with a transconductance of 24 mS/mm, limited by source and drain contacts, and an on/off current ratio of 109. fT of 28.4 GHz and fMAX of 18.5 GHz were determined from small-signal S-parameter measurements. Output power density of 0.38 W/mm was realized at 3 GHz in a power sweep using on-wafer load pull techniques.
Electric field-based frequency tuning of acoustic resonators at the material level provides an enabling technology for building complex tunable filters. Tunable acoustic resonators were fabricated in thin plates (h/λ ∼ 0.05) of X-cut lithium niobate (90°, 90°, ψ = 170°). Lithium niobate is known for its large electromechanical coupling (SH: K2 40%) and thus applicability for low-insertion loss and wideband filter applications. We demonstrate the effect of a DC bias to shift the resonant frequency by 0.4% by directly tuning the resonator material. The mechanism is based on the nonlinearities that exist in the piezoelectric properties of lithium niobate. Devices centered at 332 MHz achieved frequency tuning of 12 kHz/V through application of a DC bias.
Maximum power handling, spike leakage, and failure mechanisms have been characterized for limiters based on the thermally triggered metal-insulator transition of vanadium dioxide. These attributes are determined by properties of the metal-insulator material such as on/off resistance ratio, geometric properties that determine the film resistance and the currentcarrying capability of the device, and thermal properties such as heatsinking and thermal coupling. A limiter with greater than 10 GHz of bandwidth demonstrated 0.5 dB loss, 27 dBm threshold power, 8 Watts blocking power, and 0.4 mJ spike leakage at frequencies near 2 GHz. A separate limiter optimized for high power blocked over 60 Watts of incident power with leakage less than 25 dBm after triggering. The power handling demonstrates promise for these limiter devices, and device optimization presents opportunities for additional improvement in spike leakage, response speed, and reliability.