Publications

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High density interconnects are required for increased input/output for microelectronics applications, incentivizing the development of Cu electrochemical deposition (ECD) processes for high aspect ratio through-silicon vias (TSVs). This work outlines Cu ECD processes for 62.5 μm diameter TSVs, etched into a 625 μm thick silicon substrate, a 10:1 aspect ratio. Cu ECD in high aspect ratio features relies on a delicate balance of electrolyte composition, solution replenishment, and applied voltage. Implementing a CuSO4-H2SO4 electrolyte, which contains suppressor and a low chloride concentration, allows for a tunable relationship between applied voltage and localized deposition in the vias. A stepped potential waveform was applied to move the Cu growth front from the bottom of the via to the top. Sample characterization was performed through mechanical cross-sections and X-ray computed tomography (CT) scans. The CT scans revealed small seam voids in the Cu electrodeposit, and process parameters were tuned accordingly to produce void-free Cu features. During the voltage-controlled experiments, measured current data showed a characteristic current minimum, which was identified as an endpoint detection method for Cu deposition in these vias. We believe this is the first report of this novel endpoint detection method for TSV filling.

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Through-silicon vias (TSVs) are a critical technology for three-dimensional integrated circuit technology. These through-substrate interconnects allow electronic devices to be stacked vertically for a broad range of applications and performance improvements such as increased bandwidth, reduced signal delay, improved power management, and smaller form-factors. There are many interdependent processing steps involved in the successful integration of TSVs. This article provides a tutorial style review of the following semiconductor fabrication process steps that are commonly used in forming TSVs: deep etching of silicon to form the via, thin film deposition to provide insulation, barrier, and seed layers, electroplating of copper for the conductive metal, and wafer thinning to reveal the TSVs. Recent work in copper electrochemical deposition is highlighted, analyzing the effect of accelerator and suppressor additives in the electrolyte to enable void-free bottom-up filling from a conformally lined seed metal.

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In this paper, a closed-form mathematic equation that governs gas ingression of hermetic packages is derived from first principles and applied to moist air and water vapor ingression conditions. The equation models internal gas partial pressure change as a function of time, external conditions, and package characteristics. The equation provides the theoretical basis for direct comparisons of ingression behaviors of different gases into hermetic packages. Comparing the rates of internal air pressure increase due to air ingression and water vapor partial pressure buildup due to water vapor ingression, the authors theorize that vacuum decay may present a greater challenge to the performance of microelectromechanical systems (MEMS) devices within hermetic packages than that of water vapor content induced corrosion failures. This paper also examines gas ingression of hermetic enclosures with multiple layers of seals.

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This work demonstrates void-free Cu filling of millimeter size Through Silicon Vias (mm-TSV) in an acid copper sulfate electrolyte using a combination of a polyoxamine suppressor and chloride, analogous to previous work filling TSV that were an order of magnitude smaller in size. For high chloride concentration (i.e., 1 mmol/L) bottom-up deposition is demonstrated with the growth front being convex in shape. Instabilities in filling profile arise as the growth front approaches the freesurface due to non-uniform coupling with electrolyte hydrodynamics Filling is negatively impacted by large lithography-induced reentrant notches that increase the via cross section at the bottom. In contrast, deposition from low chloride electrolytes, proceeds with a passive-active transition on the via sidewalls. For a given applied potential the location of the transition is fixed in time and the growth front is concave in nature reflecting the gradient in chloride surface coverage. Application of a suitable potential wave form enables the location of the sidewall transition to be advanced thereby giving rise to void-free filling of the TSV.

An electrodeposition process for void-free bottom-up filling of sub-millimeter scale through silicon vias (TSVs) with Cu is detailed. The 600 μm deep and nominally 125 μm diameter metallized vias were filled with Cu in less than 7 hours under potentiostatic control. The electrolyte is comprised of 1.25 mol/L CuSO4 - 0.25 mol/L CH3SO3H with polyether and halide additions that selectively suppress metal deposition on the free surface and side walls. A brief qualitative discussion of the procedures used to identify and optimize the bottom-up void-free feature filling is presented.

A methanesulfonic acid (MSA) electrolyte with a single suppressor additive was used for potentiostatic bottom-up filling of copper in mesoscale through silicon vias (TSVs). Conversly, galvanostatic deposition is desirable for production level full wafer plating tools as they are typically not equipped with reference electrodes which are required for potentiostatic plating. Potentiostatic deposition was used to determine the over-potential required for bottom-up TSV filling and the resultant current was measured to establish a range of current densities to investigate for galvanostatic deposition. Galvanostatic plating conditions were then optimized to achieve void-free bottom-up filling in mesoscale TSVs for a range of sample sizes.

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