Publications

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Here we report on AlGaN high electron mobility transistor (HEMT)-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature-dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data (from 30°C to 500°C) revealed the reference GaN-channel HEMT experienced a 6.9x reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200-nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.

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We report on AlGaN HEMT-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data revealed the GaN-channel HEMT experienced a 6.9× reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200 nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.

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This project developed prototype germanium telluride switches, which can be used in RF applications to improve SWAP (size, weight, and power) and signal quality in RF systems. These switches can allow for highly reconfigurable systems, including antennas, communications, optical systems, phased arrays, and synthetic aperture radar, which all have high impact on current National Security goals for improved communication systems and communication technology supremacy. The final result of the project was the demonstration of germanium telluride RF switches, which could act as critical elements necessary for a single chip RF communication system that will demonstrate low SWAP and high reconfigurability

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Surging interest in engineering quantum computers has stimulated significant and focused research on technologies needed to make them manufacturable and scalable. In the ion trap realm this has led to a transition from bulk three-dimensional macro-scale traps to chip-based ion traps and included important demonstrations of passive and active electronics, waveguides, detectors, and other integrated components. At the same time as these technologies are being developed the system sizes are demanding more ions to run noisy intermediate scale quantum (NISQ) algorithms, growing from around ten ions today to potentially a hundred or more in the near future. To realize the size and features needed for this growth, the geometric and material design space of microfabricated ion traps must expand. In this paper we describe present limitations and the approaches needed to overcome them, including how geometric complexity drives the number of metal levels, why routing congestion affects the size and location of shunting capacitors, and how RF power dissipation can limit the size of the trap array. We also give recommendations for future research needed to accommodate the demands of NISQ scale ion traps that are integrated with additional technologies.

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Plasmas formed in microscale gaps at DC and plasmas formed at radiofrequency (RF) both deviate in behavior compared to the classical Paschen curve, requiring lower voltage to achieve breakdown due to unique processes and dynamics, such as field emission and controlled rates of electron/ion interactions. Both regimes have been investigated independently, using high precision electrode positioning systems for microscale gaps or large, bulky emitters for RF. However, no comprehensive study of the synergistic phenomenon between the two exists. The behavior in such a combined system has the potential to reach sub-10 V breakdown, which combined with the unique electrical properties of microscale plasmas could enable a new class of RF switches, limiters and tuners.This work describes the design and fabrication of novel on-wafer microplasma devices with gaps as small as 100 nm to be operated at GHz frequencies. We used a dual-sacrificial layer process to create devices with microplasma gaps integrated into RF compatible 50 Ω coplanar waveguide transmission lines, which will allow this coupled behaviour to be studied for the first time. These devices are modelled using conventional RF simulations as well as the Sandia code, EMPIRE, which is capable of modelling the breakdown and formation of plasma in microscale gaps driven by high frequencies. Synchronous evaluation of the modelled electrical and breakdown behaviour is used to define device structures, predict behaviour and corroborate results. We further report preliminary independent testing of the microscale gap and RF behaviour. DC testing shows modified-Paschen curve behaviour for plasma gaps at and below four microns, demonstrating decreased breakdown voltage with reduced gap size. Additionally, preliminary S-parameter measurements of as-prepared and connectorized devices have elucidated RF device behaviour. Together, these results provide baseline data that enables future experiments as well as discussion of projected performance and applications for these unique devices.

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