Publications

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Characterizing interface trap states in commercial wide bandgap devices using frequency-based measurements requires unconventionally high probing frequencies to account for both fast and slow traps associated with wide bandgap materials. The C − ψ S technique has been suggested as a viable quasi-static method for determining the interface trap state densities in wide bandgap systems, but the results are shown to be susceptible to errors in the analysis procedure. This work explores the primary sources of errors present in the C − ψ S technique using an analytical model that describes the apparent response for wide bandgap MOS capacitor devices. Measurement noise is shown to greatly impact the linear fitting routine of the 1 / C S ∗ 2 vs ψ S plot to calibrate the additive constant in the surface potential/gate voltage relationship, and an inexact knowledge of the oxide capacitance is also shown to impede interface trap state analysis near the band edge. In addition, a slight nonlinearity that is typically present throughout the 1 / C S ∗ 2 vs ψ S plot hinders the accurate estimation of interface trap densities, which is demonstrated for a fabricated n-SiC MOS capacitor device. Methods are suggested to improve quasi-static analysis, including a novel method to determine an approximate integration constant without relying on a linear fitting routine.

This paper describes a process for forming a buried field shield in GaN by an etch-and-regrowth process, which is intended to protect the gate dielectric from high fields in the blocking state. GaN trench MOSFETs made at Sandia serve as the baseline to show the limitations in making a trench gated device without a method to protect the gate dielectric. Device data coupled with simulations show device failure at 30% of theoretical breakdown for devices made without a field shield. Implementation of a field shield reduces the simulated electric field in the dielectric to below 4 MV/cm at breakdown, which eliminates the requirement to derate the device in order to protect the dielectric. For realistic lithography tolerances, however, a shield-to-channel distance of 0.4 μm limits the field in the gate dielectric to 5 MV/cm and requires a small margin of device derating to safeguard a long-term reliability and lifetime of the dielectric.

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Structural modularity is critical to solid-state transformer (SST) and solid-state power substation (SSPS) concepts, but operational aspects related to this modularity are not yet fully understood. Previous studies and demonstrations of modular power conversion systems assume identical module compositions, but dependence on module uniformity undercuts the value of the modular framework. In this project, a hierarchical control approach was developed for modular SSTs which achieves system-level objectives while ensuring equitable power sharing between nonuniform building block modules. This enables module replacements and upgrades which leverage circuit and device technology advancements to improve system-level performance. The functionality of the control approach is demonstrated in detailed time-domain simulations. Results of this project provide context and strategic direction for future LDRD projects focusing on technologies supporting the SST crosscut outcome of the resilient energy systems mission campaign.

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