Publications

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The last two decades have seen an explosion in worldwide R&D, enabling fundamentally new capabilities while at the same time changing the international technology landscape. The advent of technologies for continued miniaturization and electronics feature size reduction, and for architectural innovations, will have many technical, economic, and national security implications. It is important to anticipate possible microelectronics development directions and their implications on US national interests. This report forecasts and assesses trends and directions for several potentially disruptive microfabrication capabilities and device architectures that may emerge in the next 5-10 years.

The last two decades have seen an explosion in worldwide R&D, enabling fundamentally new capabilities while at the same time changing the international technology landscape. The advent of technologies for continued miniaturization and electronics feature size reduction, and for architectural innovations, will have many technical, economic, and national security implications. It is important to anticipate possible microelectronics development directions and their implications on US national interests. This report forecasts and assesses trends and directions for several potentially disruptive microfabrication capabilities and device architectures that may emerge in the next 5-10 years.

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Physical unclonable functions (PUFs) make use of the measurable intrinsic randomness of physical systems to establish signatures for those systems. PUFs provide a means to generate unique keys that don't need to be stored in nonvolatile memory, and they offer exciting opportunities for new authentication and supply chain security technologies.

We are using the DoD MIL-STD as our guide for microelectronics aging (MIL-STD 883J, Method 1016.2: Life/Reliability Characterization Tests). In that document they recommend aging at 3 temperatures between 200-300C, separated by at least 25C, with the supply voltage at the maximum recommended voltage for the devices at 125C (3.6V in our case). If that voltage causes excessive current or power then it can be reduced and the duration of the tests extended. The MIL-STD also recommends current limiting resistors in series with the supply. Since we don’t have much time and we may not have enough ovens and other equipment, two temperatures separated by at least 50C would be an acceptable backup plan. To ensure a safe range of conditions is used, we are executing 24-hour step tests. For these, we will apply the stress for 24 hours and then measure the device to make sure it wasn’t damaged. During the stress the PUFs should be exercised, but we don’t need to measure their response. Rather, at set intervals our devices should be returned to nominal temperature (under bias), and then measured. The MIL-STD puts these intervals at 4, 8, 16, 32, 64, 128, 256, 512 and 1000 hours, although the test can be stopped early if 75% of the devices have failed. A final recommendation per the MIL-STD is that at least 40 devices should be measured under each condition. Since we only have 25 parts, we will place 10 devices in each of two stress conditions.

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This paper presents a novel 3D structured ASIC platform that lowers the development effort required to deploy 3D integration technologies in cost sensitive, low-volume applications. The key advantage of this structured 3D ASIC architecture, over custom 3D ASICs, is a fixed vertical interconnect pattern that is programmed by a single 2D metal-via mask, allowing individual die levels to be rapidly designed, fabricated, and assembled. The first silicon realization of this architecture is a 3D-stackable 12×12mm structured ASIC die with 42K interconnects, which is resource compatible with an existing 2D structured ASIC device of the same size. 3D die stacks built using this platform are also intended to be a less costly and more flexible replacement for a large 20×20mm monolithically integrated structured ASIC device. This 3D structured ASIC platform was des igned and fabricated in Sandia's 0.35-μm foundry, and high-density front-end-of-line through silicon vias (TSVs) were developed to implement the 3D vertical interconnects.1 © 2013 IEEE.

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Vapor phase XeF{sub 2} has been used in the fabrication of various types of devices including MEMS, resonators, RF switches, and micro-fluidics, and for wafer level packaging. In this presentation we demonstrate the use of XeF{sub 2} Si etch in conjunction with deep reactive ion etch (DRIE) to release single crystal Si structures on Silicon On Insulator (SOI) wafers. XeF{sub 2} vapor phase etching is conducive to the release of movable SOI structures due to the isotropy of the etch, the high etch selectivity to silicon dioxide (SiO{sub 2}) and fluorocarbon (FC) polymer etch masks, and the ability to undercut large structures at high rates. Also, since XeF{sub 2} etching is a vapor phase process, stiction problems often associated with wet chemical release processes are avoided. Monolithic single crystal Si features were fabricated by etching continuous trenches in the device layer of an SOI wafer using a DRIE process optimized to stop on the buried SiO{sub 2}. The buried SiO{sub 2} was then etched to handle Si using an anisotropic plasma etch process. The sidewalls of the device Si features were then protected with a conformal passivation layer of either FC polymer or SiO{sub 2}. FC polymer was deposited from C4F8 gas precursor in an inductively coupled plasma reactor, and SiO{sub 2} was deposited by plasma enhanced chemical vapor deposition (PECVD). A relatively high ion energy, directional reactive ion etch (RIE) plasma was used to remove the passivation film on surfaces normal to the direction of the ions while leaving the sidewall passivation intact. After the bottom of the trench was cleared to the underlying Si handle wafer, XeF{sub 2} was used to isotropically etch the handle Si, thus undercutting and releasing the features patterned in the device Si layer. The released device Si structures were not etched by the XeF{sub 2} due to protection from the top SiO{sub 2} mask, sidewall passivation, and the buried SiO{sub 2} layer. Optimization of the XeF{sub 2} process and the sidewall passivation layers will be discussed. The advantages of releasing SOI devices with XeF{sub 2} include avoiding stiction, maintaining the integrity of the buried SiO{sub 2}, and simplifying the fabrication flow for thermally actuated devices.

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A mesoscale dimensional artifact based on silicon bulk micromachining fabrication has been developed and manufactured with the intention of evaluating the artifact both on a high precision coordinate measuring machine (CMM) and video-probe based measuring systems. This hybrid artifact has features that can be located by both a touch probe and a video probe system with a k=2 uncertainty of 0.4 {micro}m, more than twice as good as a glass reference artifact. We also present evidence that this uncertainty could be lowered to as little as 50 nm (k=2). While video-probe based systems are commonly used to inspect mesoscale mechanical components, a video-probe system's certified accuracy is generally much worse than its repeatability. To solve this problem, an artifact has been developed which can be calibrated using a commercially available high-accuracy tactile system and then be used to calibrate typical production vision-based measurement systems. This allows for error mapping to a higher degree of accuracy than is possible with a glass reference artifact. Details of the designed features and manufacturing process of the hybrid dimensional artifact are given and a comparison of the designed features to the measured features of the manufactured artifact is presented and discussed. Measurement results from vision and touch probe systems are compared and evaluated to determine the capability of the manufactured artifact to serve as a calibration tool for video-probe systems. An uncertainty analysis for calibration of the artifact using a CMM is presented.

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In this paper, we evaluate a commercially available high density plasma chemical vapor deposition (HDP-CVD) process to grow low temperature (i.e., Tin-situ & Tepitaxy < ∼460°C) germanium epitaxy for a p+-Ge/p-Si/n+-Si NIR separate absorption and multiplication avalanche photodetectors (SAM-APD). A primary concern for SAM-APDs in this material system is that high fields will not be sustainable across a highly defective Ge/Si interface. We show Ge-Si SAM-APDs that show avalanche multiplication and avalanche breakdown. A dark current of ∼0.1 mA/cm2 and a 3.2×10-4 A/W responsivity at 1310 nm were measured at punch-through. An over 400x photocurrent multiplication was demonstrated at room temperature. These results indicate that high avalanche multiplication gain is achievable in these Ge/Si heterostructures despite the highly defective interface and therefore trap assisted tunneling through the defective Ge/Si interface is not dominant at high fields. © 2007 Materials Research Society.