Publications

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The precise patterning of front-side mesas, backside vias, and selective removal of ternary alloys are all needed for power device fabrication in the various wide bandgap (AlGaN/GaN, SiC) and ultrawide bandgap (high Al-content alloys, boron nitride, Ga2O3, diamond) semiconductor technologies. The plasma etching conditions used are generally ion-assisted because of the strong bond strengths in these materials, and this creates challenges for the choice of masks in order to have sufficient selectivity over the semiconductor and to avoid mask erosion and micromasking issues. It can also be challenging to achieve practical etch rates without creating excessive damage in the patterned surface. The authors review the optimum choices for plasma chemistries for each of the semiconductors and acknowledge the pioneering work of John Coburn, who first delineated the ion-assisted etch mechanism.

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Resonant subwavelength gratings have been designed and fabricated as wavelength-specific reflectors for application as a rotary position encoder utilizing ebeam based photolithography. The first grating design used a two-dimensional layout to provide polarization insensitivity with separate layers for the grating and waveguide. The resulting devices had excellent pattern fidelity and the resonance peaks and widths closely matched the expected results. Unfortunately, the gratings were particularly angle sensitive and etch depth errors led to shifts in the center wavelength of the resonances. A second design iteration resulted in a double grating period to reduce the angle sensitivity as well as different materials and geometry; the grating and waveguide being the same layer. The inclusion of etch stop layers provided more accurate etch depths; however, the tolerance to changes in the grating duty cycle was much tighter. Results from these devices show the effects of small errors in the pattern fidelity. The fabrication process flows for both iterations of devices will be reviewed as well as the performance of the fabricated devices. A discussion of the relative merits of the various design choices provides insight into the importance of fabrication considerations during the design stage. © 2012 SPIE.

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We report a new wafer-level packaging technology for miniature MEMS in a hermetic micro-environment. The unique and new feature of this technology is that it only uses low cost wafer-level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning steps as compared to more expensive process steps that will be required in other alternative wafer-level technologies involving thru-silicon vias or membrane lids. We have demonstrated this technology by packaging silicon-based AlN microsensors in packages of size 1.3 1.3 mm2 and 200 micrometer thick. Our initial cost analysis has shown that when mass produced with high yields, this device will cost $0.10 to $0.90. The technology involves first preparing the lid and MEMS wafers separately with the sealring metal stack of Ti/Pt/Au on the MEMS wafers and Ti/Pt/Au/Ge/Au on the lid wafers. On the MEMS wafers, the Signal/Power/Ground interconnections to the wire-bond pads are isolated from the sealring metallization by an insulating AlN layer. Prior to bonding, the lid wafers were Bosch-etched in the wirebond pad area by 120 um and in the center hermetic device cavity area by 20 um. The MEMS and the lid wafers were then aligned and bonded in vacuum or in a nitrogen environment at or above the Au-Ge Eutectic temperature, 363C. The bonded wafers were then thinned and polished first on the MEMS side and then on the lid side. The MEMS side was thinned to 100 ums with a nearly scratch-free and crack-free surface. The lid side was similarly thinned to 100 ums exposing the wire-bond pads. After thinning, a 100 um thick lid remained over the MEMS features providing a 20 um high hermetic micro-environment. Thinned MEMS/Lid wafer-level assemblies were then sawed into individual devices. These devices can be integrated into the next-level assembly either by wire-bonding or by surface mounting. The wafer-level packaging approach developed in this project demonstrated RF Feedthroughs with 0.3 dB insertion loss and adequate RF performance through 2 GHz. Pressure monitoring Pirani structures built inside the hermetic lids have demonstrated the ability to detect leaks in the package. In our preliminary development experiments, we have demonstrated 50% hermetic yields. © 2011 IEEE.

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Deep reactive ion etching (DRIE) of silicon enables high aspect ratio, deep silicon features that can be incorporated into the fabrication of microelectromechanical systems (MEMS) sensors and actuators. The DRIE process creates silicon structures and consists of three steps: conformal polymer deposition, ion sputtering, and chemical etching. The sequential three step process results in sidewalls with roughness that varies with processing conditions. This paper reports the sidewall roughness for DRIE etched MEMS as a function of trench width from 5 μm to 500 μm for a 125 μm thick device layer corresponding to aspect ratios from 25 to 0.25. Using a scanning electron microscope (SEM), the surfaces were imaged detecting an upper region exhibiting a scalloping morphology and a rougher lower region exhibiting a curtaining morphology. The height of rougher curtaining region increases linearly with aspect ratio when the etch cleared the entire device layer. The surface roughness for two trench widths: 15 μm and 100 μm were further characterized using an atomic force microscope (AFM), and RMS roughness values are reported as a function of height along the surface. The sidewall roughness varies with height and depends on the trench width. Copyright © 2011 by ASME.

Vapor phase XeF{sub 2} has been used in the fabrication of various types of devices including MEMS, resonators, RF switches, and micro-fluidics, and for wafer level packaging. In this presentation we demonstrate the use of XeF{sub 2} Si etch in conjunction with deep reactive ion etch (DRIE) to release single crystal Si structures on Silicon On Insulator (SOI) wafers. XeF{sub 2} vapor phase etching is conducive to the release of movable SOI structures due to the isotropy of the etch, the high etch selectivity to silicon dioxide (SiO{sub 2}) and fluorocarbon (FC) polymer etch masks, and the ability to undercut large structures at high rates. Also, since XeF{sub 2} etching is a vapor phase process, stiction problems often associated with wet chemical release processes are avoided. Monolithic single crystal Si features were fabricated by etching continuous trenches in the device layer of an SOI wafer using a DRIE process optimized to stop on the buried SiO{sub 2}. The buried SiO{sub 2} was then etched to handle Si using an anisotropic plasma etch process. The sidewalls of the device Si features were then protected with a conformal passivation layer of either FC polymer or SiO{sub 2}. FC polymer was deposited from C4F8 gas precursor in an inductively coupled plasma reactor, and SiO{sub 2} was deposited by plasma enhanced chemical vapor deposition (PECVD). A relatively high ion energy, directional reactive ion etch (RIE) plasma was used to remove the passivation film on surfaces normal to the direction of the ions while leaving the sidewall passivation intact. After the bottom of the trench was cleared to the underlying Si handle wafer, XeF{sub 2} was used to isotropically etch the handle Si, thus undercutting and releasing the features patterned in the device Si layer. The released device Si structures were not etched by the XeF{sub 2} due to protection from the top SiO{sub 2} mask, sidewall passivation, and the buried SiO{sub 2} layer. Optimization of the XeF{sub 2} process and the sidewall passivation layers will be discussed. The advantages of releasing SOI devices with XeF{sub 2} include avoiding stiction, maintaining the integrity of the buried SiO{sub 2}, and simplifying the fabrication flow for thermally actuated devices.

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Using a two-step method of plasma and wet chemical etching, we demonstrate smooth, vertical facets for use in Al{sub x} Ga{sub 1-x} N-based deep-ultraviolet laser-diode heterostructures where x = 0 to 0.5. Optimization of plasma-etching conditions included increasing both temperature and radiofrequency (RF) power to achieve a facet angle of 5 deg from vertical. Subsequent etching in AZ400K developer was investigated to reduce the facet surface roughness and improve facet verticality. The resulting combined processes produced improved facet sidewalls with an average angle of 0.7 deg from vertical and less than 2-nm root-mean-square (RMS) roughness, yielding an estimated reflectivity greater than 95% of that of a perfectly smooth and vertical facet.

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