Heterogeneous Integration of III-V Photonics and Silicon Electronics for Advanced Optical Microsystems
Abstract not provided.
Publications
III-V Photonics at Sandia
Abstract not provided.
Copy of Thermal Stressing of InGaP/GaAs HBTs
Abstract not provided.
Thermal Stressing of InGaP/GaAs HBTs
Abstract not provided.
Optical logic gates using interconnected photodiodes and electro-absorption modulators
Optics InfoBase Conference Papers
We demonstrate an optical gate architecture with optical isolation between input and output using interconnected PD-EAMs to perform AND and NOT functions. Waveforms for 10 Gbps AND and 40 Gbps NOT gates are shown. © 2010 Optical Society of America.
Optical AND and NOT gates at 40 Gbps using electro-absorption modulator/photodiode pairs
Abstract not provided.
Optical Logic Gates Using Interconnected Photodiodes and Electro-Absorption Modulators
Abstract not provided.
Optical AND and NOT gates at 40 Gbps using electro-absorption modulator/photodiode pairs
We demonstrate an optical gate architecture using electro-absorption modulator/photodiode pairs to perform AND and NOT functions. Optical bandwidth for both gates reach 40 GHz. Also shown are AND gate waveforms at 40 Gbps.
Pre-photolithographic GaAs surface treatment for improved photoresist adhesion during wet chemical etching and improved wet etch profiles
Results of several experiments aimed at remedying photoresist adhesion failure during spray wet chemical etching of InGaP/GaAs NPN HBTs are reported. Several factors were identified that could influence adhesion and a Design of Experiment (DOE) approach was used to study the effects and interactions of selected factors. The most significant adhesion improvement identified is the incorporation of a native oxide etch immediately prior to the photoresist coat. In addition to improving adhesion, this pre-coat treatment also alters the wet etch profile of (100) GaAs so that the reaction limited etch is more isotropic compared to wafers without surface treatment; the profiles have a positive taper in both the [011] and [011] directions, but the taper angles are not identical. The altered profiles have allowed us to predictably yield fully probe-able HBTs with 5 x 5 {micro}m emitters using 5200 {angstrom} evaporated metal without planarization.
TaN resistor process development and integration
This paper describes the development and implementation of an integrated resistor process based on reactively sputtered tantalum nitride. Image reversal lithography was shown to be a superior method for liftoff patterning of these films. The results of a response surface DOE for the sputter deposition of the films are discussed. Several approaches to stabilization baking were examined and the advantages of the hot plate method are shown. In support of a new capability to produce special-purpose HBT-based Small-Scale Integrated Circuits (SSICs), we developed our existing TaN resistor process, designed for research prototyping, into one with greater maturity and robustness. Included in this work was the migration of our TaN deposition process from a research-oriented tool to a tool more suitable for production. Also included was implementation and optimization of a liftoff process for the sputtered TaN to avoid the complicating effects of subtractive etching over potentially sensitive surfaces. Finally, the method and conditions for stabilization baking of the resistors was experimentally determined to complete the full implementation of the resistor module. Much of the work to be described involves the migration between sputter deposition tools - from a Kurt J. Lesker CMS-18 to a Denton Discovery 550. Though they use nominally the same deposition technique (reactive sputtering of Ta with N{sup +} in a RF-excited Ar plasma), they differ substantially in their design and produce clearly different results in terms of resistivity, conformity of the film and the difference between as-deposited and stabilized films. We will describe the design of and results from the design of experiments (DOE)-based method of process optimization on the new tool and compare this to what had been used on the old tool.
TaN Resistor Process Development and Integration
Abstract not provided.
Pre-Photolithographic GaAs Surface Treatment for Improved Photoresist Adhesion During Wet Chemical Etching and Improved Wet Etch Profiles
Abstract not provided.
Ku-band six-bit RF MEMS time delay network
2008 IEEE CSIC Symposium: GaAs ICs Celebrate 30 Years in Monterey, Technical Digest 2008
A six-bit time delay circuit operating from DC to 18 GHz is reported. Capacitively loaded transmission lines are used to reduce the physical length of the delay elements and shrink the die size. Additionally, selection of the reference line lengths to avoid resonances allows the replacement of series-shunt switching elements with only series elements. With through-wafer transitions and a packaging seal ring, the 7 mm x 10 mm circuit demonstrates <2.8 dB of loss and 60 ps of delay with good delay flatness and accuracy through 18 GHz. © 2008 IEEE.
SOI-Enabled MEMS Processes Lead to Novel Mechanical Optical and Atomic Physics Devices Presentation
Abstract not provided.
Final report on LDRD project : advanced optical trigger systems
Advanced optically-activated solid-state electrical switch development at Sandia has demonstrated multi-kA/kV switching and the path for scalability to even higher current/power. Realization of this potential requires development of new optical sources/switches based on key Sandia photonic device technologies: vertical-cavity surface-emitting lasers (VCSELs) and photoconductive semiconductor switch (PCSS) devices. The key to increasing the switching capacity of PCSS devices to 5kV/5kA and higher is to distribute the current in multiple parallel line filaments triggered by an array of high-brightness line-shaped illuminators. Commercial mechanically-stacked edge-emitting lasers have been used to trigger multiple filaments, but they are difficult to scale and manufacture with the required uniformity. In VCSEL arrays, adjacent lasers utilize identical semiconductor material and are lithographically patterned to the required dimensions. We have demonstrated multiple-line filament triggering using VCSEL arrays to approximate line generation. These arrays of uncoupled circular-aperture VCSELs have fill factors ranging from 2% to 30%. Using these arrays, we have developed a better understanding of the illumination requirements for stable triggering of multiple-filament PCSS devices. Photoconductive semiconductor switch (PCSS) devices offer advantages of high voltage operation (multi-kV), optical isolation, triggering with laser pulses that cannot occur accidentally in nature, low cost, high speed, small size, and radiation hardness. PCSS devices are candidates for an assortment of potential applications that require multi-kA switching of current. The key to increasing the switching capacity of PCSS devices to 5kV/5kA and higher is to distribute the current in multiple parallel line filaments triggered by an array of high-brightness line-shaped illuminators. Commercial mechanically-stacked edge-emitting lasers have been demonstrated to trigger multiple filaments, but they are difficult to scale and manufacture with the required uniformity. As a promising alternative to multiple discrete edge-emitting lasers, a single wafer of vertical-cavity surface-emitting lasers (VCSELs) can be lithographically patterned to achieve the desired layout of parallel line-shaped emitters, in which adjacent lasers utilize identical semiconductor material and thereby achieve a degree of intrinsic optical uniformity. Under this LDRD project, we have fabricated arrays of uncoupled circular-aperture VCSELs to approximate a line-shaped illumination pattern, achieving optical fill factors ranging from 2% to 30%. We have applied these VCSEL arrays to demonstrate single and dual parallel line-filament triggering of PCSS devices. Moreover, we have developed a better understanding of the illumination requirements for stable triggering of multiple-filament PCSS devices using VCSEL arrays. We have found that reliable triggering of multiple filaments requires matching of the turn-on time of adjacent VCSEL line-shaped-arrays to within approximately 1 ns. Additionally, we discovered that reliable triggering of PCSS devices at low voltages requires more optical power than we obtained with our first generation of VCSEL arrays. A second generation of higher-power VCSEL arrays was designed and fabricated at the end of this LDRD project, and testing with PCSS devices is currently underway (as of September 2008).
Ku-band Six-bit RF MEMS Time Delay Netwokr
Abstract not provided.
SOI-Enabled MEMS Processes Lead to Novel Mechanical Optical and Atomic Physics Devices
Abstract not provided.
Sandia RF MEMS Lifetesting Efforts
Abstract not provided.
Sandia RF MEMS Lifetest Efforts
Abstract not provided.
SANDIA PHOTONICS TECHNOLOGY FOR AVIONICS
Abstract not provided.
Radiation Effects in GaAs Optoelectronics
Abstract not provided.
Improved manufacturability of AlGaAs/GaAs Pnp heterojunction bipolar transistors
Abstract not provided.
Improved manufacturability of AlGaAs/GaAs Pnp heterojunction bipolar transistors
ECS Transactions
Specially designed Pnp heterojunction bipolar transistors (HBT's) in the AlGaAs/GaAs material system can offer improved radiation response over commercially-available silicon bipolar junction transistors (BJT's). To be a viable alternative to the silicon Pnp BJT, improvements to the manufacturability of the HBT were required. Utilization of a Pd/Ge/Au non-spiking ohmic contact to the base and implementation of a PECVD silicon nitride hard mask for wet etch control were the primary developments that led to a more reliable fabrication process. The implementation of the silicon nitride hard mask and the subsequent process improvements increased the average electrical yield from 43% to 90%. © The Electrochemical Society.
Final report on LDRD project :leaky-mode VCSELs for photonic logic circuits
This report describes the research accomplishments achieved under the LDRD Project ''Leaky-mode VCSELs for photonic logic circuits''. Leaky-mode vertical-cavity surface-emitting lasers (VCSELs) offer new possibilities for integration of microcavity lasers to create optical microsystems. A leaky-mode VCSEL output-couples light laterally, in the plane of the semiconductor wafer, which allows the light to interact with adjacent lasers, modulators, and detectors on the same wafer. The fabrication of leaky-mode VCSELs based on effective index modification was proposed and demonstrated at Sandia in 1999 but was not adequately developed for use in applications. The aim of this LDRD has been to advance the design and fabrication of leaky-mode VCSELs to the point where initial applications can be attempted. In the first and second years of this LDRD we concentrated on overcoming previous difficulties in the epitaxial growth and fabrication of these advanced VCSELs. In the third year, we focused on applications of leaky-mode VCSELs, such as all-optical processing circuits based on gain quenching.
MEMS lifetime test setup
Abstract not provided.
Results 1–25 of 39