Publications

Kammler, Vivian G.

Abstract not provided.

Kammler, Vivian G.

Abstract not provided.

Bauer, Todd B.; Pattengale, Nicholas D.; Hilbert, Nicholas S.; Kammler, Vivian G.

Abstract not provided.

Kammler, Vivian G.

Abstract not provided.

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017

Smith, Andrew M.; Mayo, Jackson M.; Kammler, Vivian G.; Armstrong, Robert C.; Vorobeychik, Yevgeniy

Verifying that hardware design implementations adhere to specifications is a time intensive and sometimes intractable problem due to the massive size of the system's state space. Formal methods techniques can be used to prove certain tractable specification properties; however, they are expensive, and often require subject matter experts to develop and solve. Nonetheless, hardware verification is a critical process to ensure security and safety properties are met, and encapsulates problems associated with trust and reliability. For complex designs where coverage of the entire state space is unattainable, prioritizing regions most vulnerable to security or reliability threats would allow efficient allocation of valuable verification resources. Stackelberg security games model interactions between a defender, whose goal is to assign resources to protect a set of targets, and an attacker, who aims to inflict maximum damage on the targets after first observing the defender's strategy. In equilibrium, the defender has an optimal security deployment strategy, given the attacker's best response. We apply this Stackelberg security framework to synthesized hardware implementations using the design's network structure and logic to inform defender valuations and verification costs. The defender's strategy in equilibrium is thus interpreted as a prioritization of the allocation of verification resources in the presence of an adversary. We demonstrate this technique on several open-source synthesized hardware designs.

Smith, Andrew M.; Mayo, Jackson M.; Kammler, Vivian G.; Armstrong, Robert C.; Vorobeychik, Yevgeniy V.

Abstract not provided.

Mason, John J.; Ormesher, Richard C.; Mason, John J.; Kammler, Vivian G.

This report describes a new algorithm for the joint estimation of carrier phase, symbol timing and data in a Turbo coded phase shift keyed (PSK) digital communications system. Jointly estimating phase, timing and data can give processing gains of several dB over conventional processing, which consists of joint estimation of carrier phase and symbol timing followed by estimation of the Turbo-coded data. The new joint estimator allows delay and phase locked loops (DLL/PLL) to work at lower bit energies where Turbo codes are most useful. Performance results of software simulations and of a field test are given, as are details of a field programmable gate array (FPGA) implementation that is currently in design.