Publications

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Abstract not provided.

Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

We have developed a complete process module for fabricating front end of line (FEOL) through silicon vias (TSVs). In this paper we describe the integration, which relies on using thermally deposited silicon as a sacrificial material to fill the TSV during FEOL processing, followed by its removal and replacement with tungsten after FEOL processing is complete. The uniqueness of this approach follows mainly from forming the TSVs early in the FEOL while still ultimately using metal as the via fill material. TSVs formed early in the FEOL can be formed at comparatively small diameter, high aspect ratio, and high spatial density. We have demonstrated FEOL-integrated TSVs that are 2 μm in diameter, over 45 μm deep, and on 20 μm pitch for a possible interconnect density of 250,000/cm2. Moreover, thermal oxidation of silicon can be used to form the dielectric isolation. Thermal oxidation is conformal and robust in the as-formed state. Finally, TSVs formed in the FEOL alleviate device design constraints common to vias-last integration. © 2009 IEEE.

Abstract not provided.

Abstract not provided.

A wide variety of MicroElectroMechanical Systems (MEMS) are fabricated using existing novel technologies. State-of-the art integrated circuit (IC) fabrication methods are used for the fabrication of these MEMS. The fabrication of these structures requires many process steps that include deposition, patterning, etching, and CMP. The use of CMP enables the fabrication of complex, multi-level MEMS. Similar to IC fabrication, there are concerns about non-uniformity, erosion and dishing after CMP, but because of the thickness of the materials, CMP processing issues are amplified. Unlike ICs, there is no transistor basic building block so processing must be technology specific and process development is driven by the device/system performance requirements, which are very specific to the application.

Scanning capacitance microscopy (SCM) was used to study the cross section of an operating p-channel MOSFET. We discuss the novel test structure design and the modifications to the SCM hardware that enabled us to perform SCM while applying dc bias voltages to operate the device. The results are compared with device simulations performed with DAVINCI.

This paper details the analysis of vibration monitoring for end-point control in oxide CMP processes. Two piezoelectric accelerometers were integrated onto the backside of a stainless steel polishing head of an IPEC 472 polisher. One sensor was placed perpendicular to the carrier plate (vertical) and the other parallel to the plate (horizontal). Wafers patterned with metal and coated with oxide material were polished at different speeds and pressures. Our results show that it is possible to sense a change in the vibration signal over time during planarization of oxide material on patterned wafers. The horizontal accelerometer showed more sensitivity to change in vibration amplitude compared to the vertical accelerometer for a given polish condition. At low carrier and platen rotation rates, the change in vibration signal over time at fixed frequencies decreased approximately ½ - 1 order of magnitude (over the 2 to 10 psi polish pressure ranges). At high rotation speeds, the vibration signal remained essentially constant indicating that other factors dominated the vibration signaL These results show that while it is possible to sense changes in acceleration during polishing, more robust hardware and signal processing algorithms are required to ensure its use over a wide range of process conditions.

Charge storage devices in which non-equilibrium depletion regions represent stored charge are sensitive to ionizing radiation. This results since the radiation generates electron-hole pairs that neutralize excess ionized dopant charge. Silicon structures, such as dynamic RAM or CCD cells are particularly sensitive to radiation since carrier diffusion lengths in this material are often much longer than the depletion width, allowing collection of significant quantities of charge from quasi-neutral sections of the device. For GaAs the situation is somewhat different in that minority carrier diffusion lengths are shorter than in silicon, and although mobilities are higher, we expect a reduction of radiation sensitivity as suggested by observations of reduced quantum efficiency in GaAs solar cells. Dynamic memory cells in GaAs have potential increased retention times. In this paper, we report the response of a novel GaAs dynamic memory element to transient ionizing radiation. The charge readout technique is nondestructive over a reasonable applied voltage range and is more sensitive to stored charge than a simple capacitor.