CTE (coefficient of thermal expansion) mismatch between two wafers has potential for brittle failure when large areas are bonded on top of one another (wafer to wafer or wafer to die bonds). To address this type of failure, we proposed patterning a polymer around metallic interconnects. For this project, utilized benzo cyclobutene (BCB) to form the bond and accommodate stress. For the metal interconnects, we used indium. To determine the benefits of utilizing BCB, mechanical shear testing of die bonding with just BCB were compared to die bonded just with oxide. These tests demonstrated that BCB, when cured for only 30 minutes and bonded at 200°C, the BCB was able to withstand shear forces similar to oxide. Furthermore, when the BCB did fail, it experienced a more ductile failure, allowing the silicon to crack, rather than shatter. To demonstrate the feasibility of using BCB between indium interconnects, wafers were pattered with layers of BCB with vias for indium or ENEPIG (electroless nickel, electroless palladium, immersion gold). Subsequently, these wafers were pattered with a variety of indium or ENEPIG interconnect pitches, diameters, and heights. These dies were bonded under a variety of conditions, and those that held a bond, were cross-sectioned and imaged. Images revealed that certain bonding conditions allow for interconnects and BCB to achieve a void-less bond and thus demonstrate that utilizing polymers in place of oxide is a feasible way to reduce CTE stress.
High density interconnects are required for increased input/output for microelectronics applications, incentivizing the development of Cu electrochemical deposition (ECD) processes for high aspect ratio through-silicon vias (TSVs). This work outlines Cu ECD processes for 62.5 μm diameter TSVs, etched into a 625 μm thick silicon substrate, a 10:1 aspect ratio. Cu ECD in high aspect ratio features relies on a delicate balance of electrolyte composition, solution replenishment, and applied voltage. Implementing a CuSO4-H2SO4 electrolyte, which contains suppressor and a low chloride concentration, allows for a tunable relationship between applied voltage and localized deposition in the vias. A stepped potential waveform was applied to move the Cu growth front from the bottom of the via to the top. Sample characterization was performed through mechanical cross-sections and X-ray computed tomography (CT) scans. The CT scans revealed small seam voids in the Cu electrodeposit, and process parameters were tuned accordingly to produce void-free Cu features. During the voltage-controlled experiments, measured current data showed a characteristic current minimum, which was identified as an endpoint detection method for Cu deposition in these vias. We believe this is the first report of this novel endpoint detection method for TSV filling.
Copper is a commonly used interconnect metal in microelectronic interconnects due to its exceptional electrical and thermal properties. Particularly in applications of the 2.5 and 3D integration, Cu is utilized in through-silicon-vias (TSVs) and flip chip interconnects between microelectronic chips for providing miniaturization, lower power and higher performance than current 2D packaging approaches. SnAg capped Cu pillars are a common high-density interconnect technology for flip chip bonding. For these interconnects, specific properties of the Cu surface, such as roughness and cleanliness, are an important factor in the process to ensure quality solder bumps. During electroplating, tight processing parameters must be met so that defects are avoided, and high bump uniformity is achieved. An understanding of the interactions at the solder and Cu pillar interface is needed, based on the electroplating parameters, to determine the best method for populating solder on the wafer surface. In this study, surface treatment techniques such as oxygen plasma cleaning were performed on the Cu surfaces and the SnAg plating chemistry for depositing the solder were evaluated through hull cell testing to qualitatively determine the range of current densities to investigate. It was observed that current density while plating played a large role in solder bump deposition morphology. At the higher current densities greater than 60 mA/cm2, bump height non-uniformity and dendritic growth are observed and at lower current densities, less than or equal to 60 mA/cm2, uniform, continuous bump height occurred.
Through-silicon vias (TSVs) are a critical technology for three-dimensional integrated circuit technology. These through-substrate interconnects allow electronic devices to be stacked vertically for a broad range of applications and performance improvements such as increased bandwidth, reduced signal delay, improved power management, and smaller form-factors. There are many interdependent processing steps involved in the successful integration of TSVs. This article provides a tutorial style review of the following semiconductor fabrication process steps that are commonly used in forming TSVs: deep etching of silicon to form the via, thin film deposition to provide insulation, barrier, and seed layers, electroplating of copper for the conductive metal, and wafer thinning to reveal the TSVs. Recent work in copper electrochemical deposition is highlighted, analyzing the effect of accelerator and suppressor additives in the electrolyte to enable void-free bottom-up filling from a conformally lined seed metal.
Heterogeneous Integration (HI) may enable optoelectronic transceivers for short-range and long-range radio frequency (RF) photonic interconnect using wavelength-division multiplexing (WDM) to aggregate signals, provide galvanic isolation, and reduce crosstalk and interference. Integration of silicon Complementary Metal-Oxide-Semiconductor (CMOS) electronics with InGaAsP compound semiconductor photonics provides the potential for high-performance microsystems that combine complex electronic functions with optoelectronic capabilities from rich bandgap engineering opportunities, and intimate integration allows short interconnects for lower power and latency. The dominant pure-play foundry model plus the differences in materials and processes between these technologies dictate separate fabrication of the devices followed by integration of individual die, presenting unique challenges in die preparation, metallization, and bumping, especially as interconnect densities increase. In this paper, we describe progress towards realizing an S-band WDM RF photonic link combining 180 nm silicon CMOS electronics with InGaAsP integrated optoelectronics, using HI processes and approaches that scale into microwave and millimeter-wave frequencies.
Lab based x-ray phase contrast imaging (XPCI) systems have historically focused on medical applications, but there is growing interest in material science applications for non-destructive analysis of low density materials. Extending this imaging technique to higher density materials or larger samples requires higher aspect ratio gratings, to allow the use of a higher energy x-ray source. In this work, we demonstrate the use of anisotropic silicon (Si) etching in potassium hydroxide (KOH), to achieve extremely high aspect ratio gratings. This method has been shown to be effective in fabricating deep, uniform gratings by taking advantage of the etch selectivity of differing crystalline planes of silicon. Our work has demonstrated a method for determining Si crystalline plane directions, specific to (110) Si wafers, enabling high alignment accuracy of the etch mask to these crystalline planes.
State of the art grating fabrication currently limits the maximum source energy that can be used in lab based x-ray phase contrast imaging (XPCI) systems. In order to move to higher source energies, and image high density materials or image through encapsulating barriers, new grating fabrication methods are needed. In this work we have analyzed a new modality for grating fabrication that involves precision alignment of etched gratings on both sides of a substrate, effectively doubling the thickness of the grating. We have achieved a front-to-backside feature alignment accuracy of 0.5 µm demonstrating a methodology that can be applied to any grating fabrication approach extending the attainable aspect ratios allowing higher energy lab based XPCI systems.
This work demonstrates void-free Cu filling of millimeter size Through Silicon Vias (mm-TSV) in an acid copper sulfate electrolyte using a combination of a polyoxamine suppressor and chloride, analogous to previous work filling TSV that were an order of magnitude smaller in size. For high chloride concentration (i.e., 1 mmol/L) bottom-up deposition is demonstrated with the growth front being convex in shape. Instabilities in filling profile arise as the growth front approaches the freesurface due to non-uniform coupling with electrolyte hydrodynamics Filling is negatively impacted by large lithography-induced reentrant notches that increase the via cross section at the bottom. In contrast, deposition from low chloride electrolytes, proceeds with a passive-active transition on the via sidewalls. For a given applied potential the location of the transition is fixed in time and the growth front is concave in nature reflecting the gradient in chloride surface coverage. Application of a suitable potential wave form enables the location of the sidewall transition to be advanced thereby giving rise to void-free filling of the TSV.
An electrodeposition process for void-free bottom-up filling of sub-millimeter scale through silicon vias (TSVs) with Cu is detailed. The 600 μm deep and nominally 125 μm diameter metallized vias were filled with Cu in less than 7 hours under potentiostatic control. The electrolyte is comprised of 1.25 mol/L CuSO4 - 0.25 mol/L CH3SO3H with polyether and halide additions that selectively suppress metal deposition on the free surface and side walls. A brief qualitative discussion of the procedures used to identify and optimize the bottom-up void-free feature filling is presented.
Gold deposition on rotating disk electrodes, Bi3+ adsorption on planar Au films and superconformal Au filling of trenches up to 45 μm deep are examined in Bi3+-containing Na3Au(SO3)2 electrolytes with pH between 9.5 and 11.5. Higher pH is found to increase the potential-dependent rate of Bi3+ adsorption on planar Au surfaces, shortening the incubation period that precedes active Au deposition on planar surfaces and bottom-up filling in patterned features. Decreased contact angles between the Au seeded sidewalls and bottom-up growth front also suggest improved wetting. The bottom-up filling dynamic in trenches is, however, lost at pH 11.5. The impact of Au concentration, 80 mmol/L versus 160 mmol/L Na3Au(SO3)2, on bottom-up filling is examined in trenches up to ≈ 210 μm deep with aspect ratio of depth/width ≈ 30. The microstructures of void-free, bottom-up filled trench arrays used as X-ray diffraction gratings are characterized by scanning electron microscopy (SEM) and Electron Backscatter Diffraction (EBSD), revealing marked spatial variation of the grain size and orientation within the filled features.
A methanesulfonic acid (MSA) electrolyte with a single suppressor additive was used for potentiostatic bottom-up filling of copper in mesoscale through silicon vias (TSVs). Conversly, galvanostatic deposition is desirable for production level full wafer plating tools as they are typically not equipped with reference electrodes which are required for potentiostatic plating. Potentiostatic deposition was used to determine the over-potential required for bottom-up TSV filling and the resultant current was measured to establish a range of current densities to investigate for galvanostatic deposition. Galvanostatic plating conditions were then optimized to achieve void-free bottom-up filling in mesoscale TSVs for a range of sample sizes.
The development of an electrodeposition process for cobalt/iron (CoFe) alloys with minimal oxygen concentration and controlled stoichiometry is necessary for the advancement of magnetostrictive device functionalities. CoFe alloy films were electrodeposited out of a novel chemistry onto copper test structures enabling magnetic displacement testing for magnetostriction calculations. Using a combination of additives that served as oxygen scavengers, grain refiners, and complexing agents in conjunction with a pulsed plating technique, CoFe films were synthesized at thicknesses as high as 10μm with less than 8 at% oxygen at a stoichiometry of 70-75% Co and 25-30% Fe. X-Ray diffraction (XRD) analysis confirmed that these films had a crystal structure consistent with 70% Co 30% Fe Wairuaite with a slight lattice contraction due to Co doping in the film. A novel characterization technique was used to measure the displacement of the CoFe films electrodeposited, as a function of applied magnetic bias, in order to determine the saturation magnetostriction (λS) of the material. With this chemistry and a tailored pulse plating regime, λS values as high as 172 ± 25ppm have been achieved. This is believed by the authors to be the highest reported value of magnetostriction for an electrodeposited CoFe film.
Aluminum nitride (AlN) radio frequency (RF) MEMS filters utilize piezoelectric coupling for high-performance electrical filters with frequency diversity in a small form factor. Furthermore, the compatibility of AlN with CMOS fabrication makes AlN extremely attractive from a commercial standpoint. A technological hurdle has been the ability to package these suspended resonator devices at a wafer level with high yield. In this work, we describe wafer-level packaging (WLP) of AlN MEMS RF filters in an all silicon package with solder balls on nickel vanadium / gold (NiV/Au) bond pads that are subsequently ready for flip chip bonding. For this integration scheme, we utilize a 150 mm device wafer, fabricated in a CMOS foundry, and bond at the wafer level to a cavity silicon wafer, which hermetically encapsulates each device. The cavity wafer is then uniformly plasma etched back using a deep reactive ion etcher resulting in a 100 μm thick hermetic silicon lid encapsulating each die, balled with 250 μm 90/10 Pb/Sn solder balls and finally diced into individually packaged dies. Each die can be frequency-trimmed to an exact frequency by rapid temperature annealing the stress of the metallization layers of each resonator. The resulting technology yields a completely packaged wafer of 900 encapsulated die (14 mm2 by 800 μm thick) with multiple resonators and filters at various frequencies in each package.