Passive silicon photonic waveguides are exposed to gamma radiation to understand how the performance of silicon photonic integrated circuits is affected in harsh environments such as space or high energy physics experiments. The propagation loss and group index of the mode guided by these waveguides is characterized by implementing a phase sensitive swept-wavelength interferometric method. We find that the propagation loss associated with each waveguide geometry explored in this study slightly increases at absorbed doses of up to 100 krad (Si). The measured change in group index associated with the same waveguide geometries is negligibly changed after exposure. Additionally, we show that the post-exposure degradation of these waveguides can be improved through heat treatment.
Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories' CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.
Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.
Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.
The effect of a linear accelerator's (LINAC's) microstructure (i.e., train of narrow pulses) on devices and the associated transient photocurrent models are investigated. The data indicate that the photocurrent response of Si-based RF bipolar junction transistors and RF p-i-n diodes is considerably higher when taking into account the microstructure effects. Similarly, the response of diamond, SiO2, and GaAs photoconductive detectors (standard radiation diagnostics) is higher when taking into account the microstructure. This has obvious hardness assurance implications when assessing the transient response of devices because the measured photocurrent and dose rate levels could be underestimated if microstructure effects are not captured. Indeed, the rate the energy is deposited in a material during the microstructure peaks is much higher than the filtered rate which is traditionally measured. In addition, photocurrent models developed with filtered LINAC data may be inherently inaccurate if a device is able to respond to the microstructure.
Here, the effect of a linear accelerator’s (LINAC’s) microstructure (i.e., train of narrow pulses) on devices and the associated transient photocurrent models are investigated. The data indicate that the photocurrent response of Si-based RF bipolar junction transistors and RF p-i-n diodes is considerably higher when taking into account the microstructure effects. Similarly, the response of diamond, SiO2, and GaAs photoconductive detectors (standard radiation diagnostics) is higher when taking into account the microstructure. This has obvious hardness assurance implications when assessing the transient response of devices because the measured photocurrent and dose rate levels could be underestimated if microstructure effects are not captured. Indeed, the rate the energy is deposited in a material during the microstructure peaks is much higher than the filtered rate which is traditionally measured. In addition, photocurrent models developed with filtered LINAC data may be inherently inaccurate if a device is able to respond to the microstructure.
Low-and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.
Low-and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.
We present low-energy proton single-event upset (SEU) data on a 65 nm SOI SRAM whose substrate has been completely removed. Since the protons only had to penetrate a very thin buried oxide layer, these measurements were affected by far less energy loss, energy straggle, flux attrition, and angular scattering than previous datasets. The minimization of these common sources of experimental interference allows more direct interpretation of the data and deeper insight into SEU mechanisms. The results show a strong angular dependence, demonstrate that energy straggle, flux attrition, and angular scattering affect the measured SEU cross sections, and prove that proton direct ionization is the dominant mechanism for low-energy proton-induced SEUs in these circuits.
Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. As a result, grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.
The locations of conductive regions in TaOx memristors are spatially mapped using a microbeam and Nanoimplanter by rastering an ion beam across each device while monitoring its resistance. Microbeam irradiation with 800 keV Si ions revealed multiple sensitive regions along the edges of the bottom electrode. The rest of the active device area was found to be insensitive to the ion beam. Nanoimplanter irradiation with 200 keV Si ions demonstrated the ability to more accurately map the size of a sensitive area with a beam spot size of 40 nm by 40 nm. Isolated single spot sensitive regions and a larger sensitive region that extends approximately 300 nm were observed.
The recipients of the 2014 NSREC Outstanding Conference Paper Award are Nathaniel A. Dodds, James R. Schwank, Marty R. Shaneyfelt, Paul E. Dodd, Barney L. Doyle, Michael Trinczek, Ewart W. Blackmore, Kenneth P. Rodbell, Michael S. Gordon, Robert A. Reed, Jonathan A. Pellish, Kenneth A. LaBel, Paul W. Marshall, Scot E. Swanson, Gyorgy Vizkelethy, Stuart Van Deusen, Frederick W. Sexton, and M. John Martinez, for their paper entitled "Hardness Assurance for Proton Direct Ionization-Induced SEEs Using a High-Energy Proton Beam." For older CMOS technologies, protons could only cause single-event effects (SEEs) through nuclear interactions. Numerous recent studies on 90 nm and newer CMOS technologies have shown that protons can also cause SEEs through direct ionization. Furthermore, this paper develops and demonstrates an accurate and practical method for predicting the error rate caused by proton direct ionization (PDI).
The low-energy proton energy spectra of all shielded space environments have the same shape. This shape is easily reproduced in the laboratory by degrading a high-energy proton beam, producing a high-fidelity test environment. We use this test environment to dramatically simplify rate prediction for proton direct ionization effects, allowing the work to be done at high-energy proton facilities, on encapsulated parts, without knowledge of the IC design, and with little or no computer simulations required. Proton direct ionization (PDI) is predicted to significantly contribute to the total error rate under the conditions investigated. Scaling effects are discussed using data from 65-nm, 45-nm, and 32-nm SOI SRAMs. These data also show that grazing-angle protons will dominate the PDI-induced error rate due to their higher effective LET, so PDI hardness assurance methods must account for angular effects to be conservative. As a result, we show that this angular dependence can be exploited to quickly assess whether an IC is susceptible to PDI.
Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS
Schwank, James R.; Shaneyfelt, Marty R.; Ferlet-Cavrois, Véronique; Dodd, Paul E.; Blackmore, Ewart W.; Pellish, Jonathan A.; Rodbell, Kenneth P.; Heidel, David F.; Marshall, Paul W.; LaBel, Kenneth A.; Gouker, Pascale M.; Tam, Nelson; Wong, Richard; Wen, Shi J.; Reed, Robert A.; Dalton, Scott M.; Swanson, Scot E.
Phillips, Stan D.; Moen, Kurt A.; Najafizadeh, Laleh; Diestelhorst, Ryan M.; Sutton, Akil K.; Cressler, John D.; Vizkelethy, Gyorgy; Dodd, Paul E.; Marshall, Paul W.
The amounts of charge collection by single-photon absorption to that by two-photon absorption laser testing techniques have been directly compared using specially made SOI diodes. Details of this comparison are discussed.
Large and unexpected radiation-induced voltage shifts have been observed for some MOS technologies exposed to moisture. The mechanisms for these large voltage shifts and their implications for long-term aging are discussed.
Physical mechanisms responsible for single-event effects are reviewed, concentrating on silicon MOS devices and digital integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given. Single-event upset mechanisms in SRAMs are briefly described, as is the initiation of single-event latchup in CMOS structures. Techniques for mitigating single-event effects are described, including the impact of technology trends on mitigation efficacy. Future challenges are briefly explored.
The total dose hardness of several commercial power MOSFET technologies is examined. After exposure to 20 krad(SiO{sub 2}) most of the n- and p-channel devices examined in this work show substantial (2 to 6 orders of magnitude) increases in off-state leakage current. For the n-channel devices, the increase in radiation-induced leakage current follows standard behavior for moderately thick gate oxides, i.e., the increase in leakage current is dominated by large negative threshold voltage shifts, which cause the transistor to be partially on even when no bias is applied to the gate electrode. N-channel devices biased during irradiation show a significantly larger leakage current increase than grounded devices. The increase in leakage current for the p-channel devices, however, was unexpected. For the p-channel devices, it is shown using electrical characterization and simulation that the radiation-induced leakage current increase is related to an increase in the reverse bias leakage characteristics of the gated diode which is formed by the drain epitaxial layer and the body. This mechanism does not significantly contribute to radiation-induced leakage current in typical p-channel MOS transistors. The p-channel leakage current increase is nearly identical for both biased and grounded irradiations and therefore has serious implications for long duration missions since even devices which are usually powered off could show significant degradation and potentially fail.
Microelectronic devices in satellites and spacecraft are exposed to high energy cosmic radiation. Furthermore, Earth-based electronics can be affected by terrestrial radiation. The radiation causes a variety of Single Event Effects (SEE) that can lead to failure of the devices. High energy heavy ion beams are being used to simulate both the cosmic and terrestrial radiation to study radiation effects and to ensure the reliability of electronic devices. Broad beam experiments can provide a measure of the radiation hardness of a device (SEE cross section) but they are unable to pinpoint the failing components in the circuit. A nuclear microbeam is an ideal tool to map SEE on a microscopic scale and find the circuit elements (transistors, capacitors, etc.) that are responsible for the failure of the device. In this paper a review of the latest radiation effects microscopy (REM) work at Sandia will be given. Different SEE mechanisms (Single Event Upset, Single Event Transient, etc.) and the methods to study them (Ion Beam Induced Charge (IBIC), Single Event Upset mapping, etc.) will be discussed. Several examples of using REM to study the basic effects of radiation in electronic devices and failure analysis of integrated circuits will be given.
Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallele-piped model for the sensitive volume is not applicable to this technology. A new first-order physical model is proposed and calibrated with moderate success.
This paper presents the first 3-D simulation of heavy-ion induced charge collection in a SiGe HBT, together with microbeam testing data. The charge collected by the terminals is a strong function of the ion striking position. The sensitive area of charge collection for each terminal is identified based on analysis of the device structure and simulation results. For a normal strike between the deep trench edges, most of the electrons and holes are collected by the collector and substrate terminals, respectively. For an ion strike between the shallow trench edges surrounding the emitter, the base collects appreciable amount of charge. Emitter collects negligible amount of charge. Good agreement is achieved between the experimental and simulated data. Problems encountered with mesh generation and charge collection simulation are also discussed.
We examine the total-dose radiation response of capacitors and transistors with stacked Al{sub 2}O{sub 3} on oxynitride gate dielectrics with Al and poly-Si gates after irradiation with 10 keV X-rays. The midgap voltage shift increases monotonically with dose and depends strongly on both Al{sub 2}O{sub 3} and SiO{sub x}N{sub y} thickness. The thinnest dielectrics, of most interest to industry, are extremely hard to ionizing irradiation, exhibiting only {approx}50 mV of shift at a total dose of 10 Mrad(SiO{sub 2}) for the worst case bias condition. Oxygen anneals are found to improve the total dose radiation response by {approx}50% and induce a small amount of capacitance-voltage hysteresis. Al{sub 2}O{sub 3}/SiO{sub x}N{sub y} dielectrics which receive a {approx}1000 C dopant activation anneal trap {approx}12% more of the initial charge than films annealed at 550 C. Charge pumping measurements show that the interface trap density decreases with dose up to 500 krad(SiO{sub 2}). This surprising result is discussed with respect to hydrogen effects in alternative dielectric materials, and may be the result of radiation-induced hydrogen passivation of some of the near-interfacial defects in these gate dielectrics.
It is shown that final chip passivation layers can have a significant impact on total dose hardness. A number of final chip passivation layers are evaluated to identify films that mitigate enhanced low-dose-rate sensitivity (ELDRS) in National Semiconductor Corporation's linear bipolar technologies. It is shown that devices fabricated with either a low temperature oxide or a tetraethyl ortho silicate passivation do not exhibit significant ELDRS effects up to 100 krad(SiO{sub 2}). Passivation studies on CMOS SRAMs suggest that it is unlikely that the passivation layers (or processing tools) are acting as a new source of hydrogen, which could drift or diffuse into the oxide and increase ELDRS sensitivity. Instead, it is possible that the passivation layers affect the mechanical stress in the oxide, which may affect oxide trap properties and possibly the release and mobility of hydrogen. Correlations between mechanical stress induced by the passivation layers and radiation degradation are discussed.
Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.
The effects of photocurrents in nuclear weapons induced by proximal nuclear detonations are well known and remain a serious hostile environment threat for the US stockpile. This report describes the final results of an LDRD study of the physical phenomena underlying prompt photocurrents in microelectronic devices and circuits. The goals of this project were to obtain an improved understanding of these phenomena, and to incorporate improved models of photocurrent effects into simulation codes to assist designers in meeting hostile radiation requirements with minimum build and test cycles. We have also developed a new capability on the ion microbeam accelerator in Sandia's Ion Beam Materials Research Laboratory (the Transient Radiation Microscope, or TRM) to supply ionizing radiation in selected micro-regions of a device. The dose rates achieved in this new facility approach those possible with conventional large-scale dose-rate sources at Sandia such as HERMES III and Saturn. It is now possible to test the physics and models in device physics simulators such as Davinci in ways not previously possible. We found that the physical models in Davinci are well suited to calculating prompt photocurrents in microelectronic devices, and that the TRM can reproduce results from conventional large-scale dose-rate sources in devices where the charge-collection depth is less than the range of the ions used in the TRM.
Improvements have been made at TRIUMF to permit higher proton intensities of up to 1010 cm-2s-1 over the energy range 20-500 MeV. This improved capability enables the study of displacement damage effects that require higher fluence irradiations. In addition, a high energy neutron irradiation capability has been developed for terrestrial cosmic ray soft error rate (SER) characterization of integrated circuits. The neutron beam characteristics of this facility are similar to those currently available at the Los Alamos National Laboratory WNR test facility. SER data measured on several SRAMs using the TRIUMF neutron beam are in good agreement with the results obtained on the same devices using the WNR facility. The TRIUMF neutron beam also contains thermal neutrons that can be easily removed by a sheet of cadmium. The ability to choose whether thermal neurons are present is a useful attribute not possible at the WNR.
High-energy ion-irradiated 3.3-nm oxynitride film and 2.2-nm SiO2-film MOS capacitors show premature break-down during subsequent electrical stress. This degradation in breakdown increases with increasing ion linear energy transfer (LET), increasing ion fluence, and decreasing oxide thickness. The reliability degradation due to high-energy ion-induced latent defects is explained by a simple percolation model of conduction through SiO2 layers with irradiation and/or electrical stress-induced defects. Monitoring the gate-leakage current reveals the presence of latent defects in the dielectric films. These results may be significant to future single-event effects and single-event gate rupture tests for MOS devices and ICs with ultrathin gate oxides.
The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-Dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMS, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMS is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.
Under this effort, a new method for studying the single event upset (SEU) in microelectronics has been developed and demonstrated. Called TRIBICC, for Time Resolved Ion Beam Induced Charge Collection, this technique measures the transient charge-collection waveform from a single heavy-ion strike with a {minus}.03db bandwidth of 5 GHz. Bandwidth can be expanded up to 15 GHz (with 5 ps sampling windows) by using an FFT-based off-line waveform renormalization technique developed at Sandia. The theoretical time resolution of the digitized waveform is 24 ps with data re-normalization and 70 ps without re-normalization. To preserve the high bandwidth from IC to the digitizing oscilloscope, individual test structures are assembled in custom high-frequency fixtures. A leading-edge digitized waveform is stored with the corresponding ion beam position at each point in a two-dimensional raster scan. The resulting data cube contains a spatial charge distribution map of up to 4,096 traces of charge (Q) collected as a function of time. These two dimensional traces of Q(t) can cover a period as short as 5 ns with up to 1,024 points per trace. This tool overcomes limitations observed in previous multi-shot techniques due to the displacement damage effects of multiple ion strikes that changed the signal of interest during its measurement. This system is the first demonstration of a single-ion transient measurement capability coupled with spatial mapping of fast transients.
SEU is studied in SOI transistors and circuits with various body tie structures. The importance of impact ionization effects, including single-event snapback, is explored. Implications for hardness assurance testing of SOI integrated circuits are discussed.
Large differences in charge buildup in SOI buried oxides can result between x-ray and Co-60 irradiations. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored.
Scanning capacitance microscopy (SCM) was used to study the cross section of an operating p-channel MOSFET. We discuss the novel test structure design and the modifications to the SCM hardware that enabled us to perform SCM while applying dc bias voltages to operate the device. The results are compared with device simulations performed with DAVINCI.
Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it is likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance.
Floating body effects can undermine the soft-error tolerance of partially-depleted SOI technologies [1, 2]. Body ties are used to mitigate floating body effects [3,4]. In this paper, we study the charge collection properties and effectiveness of different body tie designs for reducing soft errors induced by energetic particle strikes.
The basic mechanisms of single-event upset are reviewed, including charge collection in silicon junctions and transistors, and properties of single-event upset in CMOS static random access memory (SRAM) cells. The mechanisms are illustrated through the use of three-dimensional device and circuit simulations. Technology trends and implications for commercial devices are discussed.
The single-event upset (SEU) responses of 16 Kbit to 1 Mbit SRAMs irradiated with low and high-energy heavy ions are reported. Standard low-energy heavy ion tests appear to be sufficiently conservative for technologies down to 0.5 {micro}m.
Low-energy alpha particles emitted from packaging and high-energy heavy ions in space possess the capability of causing changes in memory state when incident on semiconductor memory cans and latch circuits. This phenomenon of single-event upset (SEU) is caused by collection of charge created as the particle travels through a sensitive volume of the device. As devices are continually down-sized, the corresponding decrease in amount of charge held on storage nodes increases device susceptibility to SEU. Solutions to harden devices to SEU require an in-depth understanding of the basic mechanisms responsible for upset. Also, a detailed understanding of the charge-collection volume is critical for predicting on-orbit error rates. Previous work has revealed the formation of a field funnel in response to the particle strike. Analytical models that treat the funnel in a time-averaged sense have been developed, and have been reasonably successful at predicting total collected charge for particles with low linear energy transfer (LET). Sophisticated two- and three-dimensional simulations have been used to investigate the funneling process more rigorously; however, the interplay between the funnel and collection by drift and diffusion has remained somewhat obscure. In this paper, we present an examination of fundamental charge-collection mechanisms and the role of the funnel, using advanced three-dimensional drift-diffusion modeling. We then apply the insight gained to address radiation hardness issues in light of current technology trends.