Publications

This conference presents the recipients of the Outstanding Conference Paper Award from the 2015 IEEE Nuclear and Space Radiation Effects Conference.

Low-and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.

Low-and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.

We present low-energy proton single-event upset (SEU) data on a 65 nm SOI SRAM whose substrate has been completely removed. Since the protons only had to penetrate a very thin buried oxide layer, these measurements were affected by far less energy loss, energy straggle, flux attrition, and angular scattering than previous datasets. The minimization of these common sources of experimental interference allows more direct interpretation of the data and deeper insight into SEU mechanisms. The results show a strong angular dependence, demonstrate that energy straggle, flux attrition, and angular scattering affect the measured SEU cross sections, and prove that proton direct ionization is the dominant mechanism for low-energy proton-induced SEUs in these circuits.

Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. As a result, grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.

Abstract not provided.

Abstract not provided.

The recipients of the 2014 NSREC Outstanding Conference Paper Award are Nathaniel A. Dodds, James R. Schwank, Marty R. Shaneyfelt, Paul E. Dodd, Barney L. Doyle, Michael Trinczek, Ewart W. Blackmore, Kenneth P. Rodbell, Michael S. Gordon, Robert A. Reed, Jonathan A. Pellish, Kenneth A. LaBel, Paul W. Marshall, Scot E. Swanson, Gyorgy Vizkelethy, Stuart Van Deusen, Frederick W. Sexton, and M. John Martinez, for their paper entitled "Hardness Assurance for Proton Direct Ionization-Induced SEEs Using a High-Energy Proton Beam." For older CMOS technologies, protons could only cause single-event effects (SEEs) through nuclear interactions. Numerous recent studies on 90 nm and newer CMOS technologies have shown that protons can also cause SEEs through direct ionization. Furthermore, this paper develops and demonstrates an accurate and practical method for predicting the error rate caused by proton direct ionization (PDI).

The low-energy proton energy spectra of all shielded space environments have the same shape. This shape is easily reproduced in the laboratory by degrading a high-energy proton beam, producing a high-fidelity test environment. We use this test environment to dramatically simplify rate prediction for proton direct ionization effects, allowing the work to be done at high-energy proton facilities, on encapsulated parts, without knowledge of the IC design, and with little or no computer simulations required. Proton direct ionization (PDI) is predicted to significantly contribute to the total error rate under the conditions investigated. Scaling effects are discussed using data from 65-nm, 45-nm, and 32-nm SOI SRAMs. These data also show that grazing-angle protons will dominate the PDI-induced error rate due to their higher effective LET, so PDI hardness assurance methods must account for angular effects to be conservative. As a result, we show that this angular dependence can be exploited to quickly assess whether an IC is susceptible to PDI.

The effect of proton energy on single-event latchup (SEL) in present-day SRAMs is investigated over a wide range of proton energies and temperature. SRAMs from five different vendors were irradiated at proton energies from 20 to 500 MeV and at temperatures of 25° and 85°C. For the SRAMs and radiation conditions examined in this work, proton energy SEL thresholds varied from as low as 20 MeV to as high as 490 MeV. To gain insight into the observed effects, the heavy-ion SEL linear energy transfer (LET) thresholds of the SRAMs were measured and compared to high-energy transport calculations of proton interactions with different materials. For some SRAMs that showed proton-induced SEL, the heavy-ion SEL threshold LET was as high as 25 MeV-cm 2/mg. Proton interactions with Si cannot generate nuclear recoils with LETs this large. Our nuclear scattering calculations suggest that the nuclear recoils are generated by proton interactions with tungsten. Tungsten plugs are commonly used in most high-density ICs fabricated today, including SRAMs. These results demonstrate that for system applications where latchups cannot be tolerated, SEL hardness assurance testing should be performed at a proton energy at least as high as the highest proton energy present in the system environment. Moreover, the best procedure to ensure that ICs will be latchup free in proton environments may be to use a heavy-ion source with LETs ≥40 MeV-cm 2/mg. © 2005 IEEE.

Abstract not provided.

Development in the field of destructive single-event effects over the last 40 years are reviewed. Single-event latchup, single-event burnout, single-event gate rupture, and single-event snap-back are discussed beginning with the first observation of each effect, its phenomenology, and the development of present day understanding of the mechanisms involved.

Abstract not provided.

Under this effort, a new method for studying the single event upset (SEU) in microelectronics has been developed and demonstrated. Called TRIBICC, for Time Resolved Ion Beam Induced Charge Collection, this technique measures the transient charge-collection waveform from a single heavy-ion strike with a {minus}.03db bandwidth of 5 GHz. Bandwidth can be expanded up to 15 GHz (with 5 ps sampling windows) by using an FFT-based off-line waveform renormalization technique developed at Sandia. The theoretical time resolution of the digitized waveform is 24 ps with data re-normalization and 70 ps without re-normalization. To preserve the high bandwidth from IC to the digitizing oscilloscope, individual test structures are assembled in custom high-frequency fixtures. A leading-edge digitized waveform is stored with the corresponding ion beam position at each point in a two-dimensional raster scan. The resulting data cube contains a spatial charge distribution map of up to 4,096 traces of charge (Q) collected as a function of time. These two dimensional traces of Q(t) can cover a period as short as 5 ns with up to 1,024 points per trace. This tool overcomes limitations observed in previous multi-shot techniques due to the displacement damage effects of multiple ion strikes that changed the signal of interest during its measurement. This system is the first demonstration of a single-ion transient measurement capability coupled with spatial mapping of fast transients.

Electrical breakdown in thin oxides is assessed by a new bias-temperature ramp technique. No significant effect of radiation exposure on breakdown is observed for high quality thermal and nitrided oxides, up to 20 Mrad(SiO{sub 2}).

Gate oxide electric fields are expected to increase to greater than 5 MV/cm as feature size approaches 0.1 micrometers in advanced integrated circuit (IC) technologies. Work by Johnston, et al. raised the concern that single event gate rupture (SEGR) may limit the scaling of advanced ICs for space applications. SEGR has also been observed in field programmable gate arrays, which rely on thin dielectrics for electrical programming at very high electric fields. The focus of this effort is to further explore the mechanisms for SEGR in thin gate oxides. The authors examine the characteristics of heavy ion induced breakdown and compare them to ion induced damage in thin gate oxides. Further, the authors study the impact of precursor damage in oxides on SEGR threshold. Finally, they compare thermal and nitrided oxides to see if SEGR is improved by incorporating nitrogen in the oxide.

The dependence of single event gate rupture (SEGR) critical field on oxide thickness is examined for gate oxides from 6 to 18 nm. Capacitor data are compared to SEGR data from full integrated circuits. A I/ECR dependence is found for critical field to rupture as a function of ion linear energy transfer (LET), consistent with earlier work for power MOSFETS with oxide thicknesses from 30 to 150 nm. More importantly, critical field to rupture increases with decreasing oxide thickness, consistent with increasing oxide breakdown field prior to heavy-ion exposure. This suggests that SEGR need not be a limiting factor as future technologies scale into the deep submicron region. However, there is a great deal of uncertainty in how voltage may scale with decreasing oxide thickness, and SEGR may continue to be a concern for devices that operate at electric fields significantly higher than 5 MV/cm. © 1997 IEEE.

Ion-beam-induced charge-collection imaging (IBICC) has been used to study the SEU mechanisms of the Sandia TA670 16K-bit SRAM. Quantitative charge-collection spectra from known regions of the memory cell have been derived with this technique. For 2.4-MeV He ions at normal incidence, charge collection depth for a reverse-biased p+ drain strike is estimated to be 4.8±0.4 μm. Heavy-ion strikes to the reverse-biased p-well result in nearly complete collection of deposited charge to a depth of 5.5±0.5 μm. A charge amplification effect in the n-on drain is identified and is due to either bipolar amplification or a shunt effect in the parasitic vertical npn bipolar transistor associated with the n+/n substrate, p-well, and n+ drain. This effect is present only when the n+ drain is at 0V bias. When coupled with previous SEU-imaging, these results strongly suggest that the dominant SEU mechanism in this SRAM is a heavy-ion strike to the n-on transistor drain. © 1993 IEEE