Measurement and Modeling of Single Event Transients in 12nm Inverters
Abstract not provided.
Publications
Multiscale System Modeling of Single Event Induced Faults in Advanced Node Processors
Abstract not provided.
Fault Tracking and Modeling in Advanced Node Processors of Single Event Effects
Abstract not provided.
DFF Architecture Impact on SEU Response in Different Semiconductor Technologies
Abstract not provided.
Multiscale Modeling of Single Event-Induced Faults in FinFET-based Processors
Abstract not provided.
DFF Layout Variations in CMOS SOI -Analysis of Hardening by Design Options
IEEE Transactions on Nuclear Science
Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories' CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.
Modeling and Simulation Approaches to Single-Event Effects in Microelectronics
Abstract not provided.
Impact of interface quality on single-event charge collection in SOI technologies
Abstract not provided.
DFF Layout Variations in CMOS SOI ? Analysis of Hardening by Design Options
Abstract not provided.
Using MRED to Screen Multiple-Node Charge-Collection Mitigated SOI Layouts
IEEE Transactions on Nuclear Science
Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.
Using MRED to Screen Multiple Node Charge Collection Mitigated SOI Layouts
Abstract not provided.
A Rad-Hard eFPGA Core for Reconfigurable System-On-Chips
Abstract not provided.
A Rad-Hard eFPGA Core for Reconfigurable System-On-Chips
Abstract not provided.
Single Event Effects in Sandia's CMOS7 Devices and Acceptance Testing in Integrated Circuits
Abstract not provided.
Outstanding Conference Paper Award: 2015 IEEE Nuclear and Space Radiation Effects Conference
IEEE Transactions on Nuclear Science
This conference presents the recipients of the Outstanding Conference Paper Award from the 2015 IEEE Nuclear and Space Radiation Effects Conference.
New insights gained on mechanisms of low-energy proton-induced SEUs by minimizing energy straggle
IEEE Transactions on Nuclear Science
In this study, we present low-energy proton single-event upset (SEU) data on a 65 nm SOI SRAM whose substrate has been completely removed. Since the protons only had to penetrate a very thin buried oxide layer, these measurements were affected by far less energy loss, energy straggle, flux attrition, and angular scattering than previous datasets. The minimization of these common sources of experimental interference allows more direct interpretation of the data and deeper insight into SEU mechanisms. The results show a strong angular dependence, demonstrate that energy straggle, flux attrition, and angular scattering affect the measured SEU cross sections, and prove that proton direct ionization is the dominant mechanism for low-energy proton-induced SEUs in these circuits.
The contribution of low-energy protons to the total on-orbit SEU rate
IEEE Transactions on Nuclear Science
Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. As a result, grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.
The contribution of low-energy protons to the total on-orbit SEU rate
Abstract not provided.
New insights gained on mechanisms of low-energy proton-induced SEUs by minimizing energy straggle
Abstract not provided.
Single Event Effects Testing Results in Sandia National Laboratories Via Programmable ASIC Platforms
Abstract not provided.
Reduced Complexity RHBD Logic Cells for 32-nm SOI ASICs
Abstract not provided.
Reduced Complexity RHBD Logic Cells for 32-nm SOI ASICs
Abstract not provided.
Six Generations of ViArray Rad-Hard Structured ASICs
Abstract not provided.
23 Results