Publications

Abstract not provided.

The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-Dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMS, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMS is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

Metal-oxide-silicon capacitors fabricated in a bi-polar process were examined for densities of oxide trapped charge, interface traps and deactivated substrate acceptors following high-dose-rate irradiation at 100 C. Acceptor neutralization near the Si surface occurs most efficiently for small irradiation biases in depletion. The bias dependence is consistent with compensation and passivation mechanisms involving the drift of H{sup +} ions in the oxide and Si layers and the availability of holes in the Si depletion region. Capacitor data from unbiased irradiations were used to simulate the impact of acceptor neutralization on the current gain of an npn bipolar transistor. Neutralized acceptors near the base surface enhance current gain degradation associated with radiation-induced oxide trapped charge and interface traps by increasing base recombination. The additional recombination results from the convergence of carrier concentrations in the base and increased sensitivity of the base to oxide trapped charge. The enhanced gain degradation is moderated by increased electron injection from the emitter. These results suggest that acceptor neutralization may enhance radiation-induced degradation of linear circuits at elevated temperatures.

Abstract not provided.

Abstract not provided.

An improved charge separation technique for metal-oxide-silicon (MOS) capacitors is presented which accounts for the deactivation of substrate dopants by hydrogen at elevated irradiation temperatures or small irradiation biases. Using high-frequency capacitance-voltage measurements, radiation-induced inversion voltage shifts are separated into components due to oxide trapped charge, interface traps, and deactivated dopants, where the latter is computed from a reduction in Si capacitance. In the limit of no radiation-induced dopant deactivation, this approach reduces to the standard midgap charge separation technique used widely for the analysis of room-temperature irradiations. The technique is demonstrated on a p-type MOS capacitor irradiated with 60Co γ rays at 100°C and zero bias, where the dopant deactivation is significant. © 2000 American Institute of Physics.

Dopant deactivation at 100 C is measured in bipolar Si-SiO{sub 2} structures as a function of irradiation bias. The deactivation occurs most efficiently at small biases in depletion and is consistent with passivation and compensation mechanisms involving hydrogen.

SEU is studied in SOI transistors and circuits with various body tie structures. The importance of impact ionization effects, including single-event snapback, is explored. Implications for hardness assurance testing of SOI integrated circuits are discussed.

Thermal-stress effects are shown to have a significant impact on the enhanced low-dose-rate sensitivity of linear bipolar circuits. Implications of these results on hardness assurance testing and mechanisms are discussed.

Electrical breakdown in thin oxides is assessed by a new bias-temperature ramp technique. No significant effect of radiation exposure on breakdown is observed for high quality thermal and nitrided oxides, up to 20 Mrad(SiO{sub 2}).

The natural space radiation environment presents a great challenge to present and future satellite systems with significant assets in space. Defining requirements for such systems demands knowledge about the space radiation environment and its effects on electronics and optoelectronics technologies, as well as suitable risk assessment of the uncertainties involved. For mission of high radiation levels, radiation-hardened integrated circuits will be required to preform critical mission functions. The most successful systems in space will be those that are best able to blend standard commercial electronics with custom radiation-hardened electronics in a mix that is suitable for the system of interest.

Abstract not provided.

This paper addresses key issues for the cost-effective use of COTS (Commercially available Off The Shelf) microelectronics in radiation environments that enable circuit or system designers to manage risks and ensure mission success. We review several factors and tradeoffs affecting the successful application of COTS parts including (1) hardness assurance and qualification issues, (2) system hardening techniques, and (3) life-cycle costs. The paper also describes several experimental studies that address trends in total-dose, transient, and single-event radiation hardness as COTS technology scales to smaller feature sizes. As an example, the level at which dose-rate upset occurs in Samsung SRAMs increases from 1.4x10s rad(Si)/s for a 256K SRAM to 7.7xl09rad(Si)/s for a 4M SRAM, indicating unintentional hardening improvements in the design or process of a commercial technology. Additional experiments were performed to quantify variations in radiation hardness for COTS parts. In one study, only small (10-15%) variations were found in the dose-rate upset and latchup thresholds for Samsung 4M SRAMs from three different date codes. In another study, irradiations of 4M SRAMs from Samsung, Hitachi, and Toshiba indicate large differences in total-dose radiation hardness. The paper attempts to carefully define terms and clear up misunderstandings about the definitions of "COTS'1 and "radiation-hardened (RH)" technology. © 1999 IEEE.

An improved standard total-dose test method is described to qualify electronics for a low-dose radiation environment typical of space systems. The method consists of {sup 60}Co irradiation at a dose rate of 1--3 Gy(Si)/s (100--300 rad(Si)/s) and a subsequent 373 K (100{degree}C) bake. New initiatives in radiation hardness assurance are also briefly discussed, including the Qualified Manufacturers List (QML) test methodology and the possible use of 1/f noise measurements as a nondestructive screen for oxide-trap charge related failure. 8 refs.

Statistical process control (SPC) of technology parameters relevant to radiation hardness, test structure to IC correlation, and extrapolation from laboratory to threat scenarios are keys to implementing QML for radiation hardness assurance in a cost-effective manner. Data from approximately 300 wafer lots fabricated in Sandia's 4/3-µm and CMOS IIIA (2-µm) technologies are used to demonstrate approaches to, and highlight issues associated with, implementing QML for radiation-hardened CMOS in space applications. An approach is demonstrated to implement QML for single-event upset (SEU) immunity on 16k SRAMs that involves relating values of feedback resistance to system error rates. It is seen that the process capability indices, Cp and Cpk, for the manufacture of 400 kΩ feedback resistors required to provide SEU tolerance do not conform to “6σ” quality standards. For total-dose, ΔVit shifts measured on transistors are correlated with circuit response in the space environment. SPC is illustrated for ΔVit, and violations of SPC rules are interpreted in terms of continuous improvement. Finally, design validation for SEU, and quality conformance inspections for total-dose, are identified as major obstacles to cost-effective QML implementation. Techniques and tools that will help QML provide real cost savings are identified as physical models, 3D device-plus-circuit codes, and improved design simulators. © 1990 IEEE