This abstract presents a comprehensive analysis of total ionizing dose (TID) response in GlobalFoundries' (GFs) 12LP 12 nm bulk Fin-based field effect transistor (FinFET) technology using 10 keV X-rays. Devices with higher threshold voltages (VTs) demonstrated lower increases in OFF-state leakage current (I_ DS, OFF ) post-irradiation, highlighting the mitigating role of high VT in TID response. Our data show that transistors with fewer fins exhibit superior TID resistance, implying lower susceptibility to radiation effects. Our study also probed two bias conditions, 'Gate-On' and 'Pass-Gate,' with the former displaying more severe TID degradation. Interestingly, p-type devices displayed negligible degradation, underscoring their inherent resilience to TID effects. Additionally, medium thick n-type devices echoed the fin-count-dependent TID response observed in other transistor types, further strengthening our findings. These results underscore the importance of strategic transistor selection and design for enhancing the TID resilience of future complementary metal-oxide semiconductor (CMOS) FinFET architectures, particularly critical in radiation-intense environments.
Teng, Jeffrey W.; Nergui, Delgermaa; Parameswaran, Hari; Sepulveda-Ramos, Nelson E.; Tzintzarov, George N.; Mensah, Yaw; Cheon, Clifford D.; Rao, Sunil G.; Ringel, Brett; Gorchichko, Mariia; Li, Kan; Ying, Hanbin; Ildefonso, Adrian; Dodds, Nathaniel A.; Nowlin, Robert N.; Zhang, En X.; Fleetwood, Daniel M.; Cressler, John D.
Integrated silicon microwave pin diodes are exposed to 10-keV X-rays up to a dose of 2 Mrad(SiO2) and 14-MeV fast neutrons up to a fluence of 2.2, × ,10,^ 13 cm-2. Changes in both dc leakage current and small-signal circuit components are examined. Degradation in performance due to total-ionizing dose (TID) is shown to be suppressed by non-quasi-static (NQS) effects during radio frequency (RF) operation. Tolerance to displacement damage from fast neutrons is also observed, which is explained using technology computer-aided design (TCAD) simulations. Overall, the characterized pin diodes are tolerant to cumulative radiation at levels consistent with space applications such as geosynchronous weather satellites.
Soft error rates (SER) are characterized for the 5-nm bulk FinFET D flip-flops for alpha particles, thermal neutrons, and high-energy neutrons as a function of supply voltage. At nominal operating voltage, the 5-nm node has higher SER than the 7-nm node for all three particle types, with increases of 148%, 168%, and 26%, respectively. The overall SER for the 5-nm node was ~2X greater than that of the 7-nm node, because the reduction in critical charge was higher than that in collected charge. For alpha particle exposures, temperature effects on SER were more prominent for the 5-nm node than both the 7-nm and 16-nm node. Relative contribution of alpha particle SER increases with scaling, and it accounts for 13% of the overall SER at the 5-nm node.
Teng, Jeffrey W.; Nergui, Delgermaa; Sepulveda-Ramos, Nelson E.; Tzintzarov, George N.; Mensah, Yaw; Cheon, Clifford D.; Rao, Sunil G.; Ringel, Brett; Gorchichko, Mariia; Li, Kan; Ying, Hanbin; Ildefonso, Adrian; Dodds, Nathaniel A.; Nowlin, Robert N.; Zhang, En X.; Fleetwood, Daniel M.; Cressler, John D.
Here, integrated silicon microwave pin diodes are exposed to 10-keV X-rays up to a dose of 2 Mrad(SiO2) and 14-MeV fast neutrons up to a fluence of 2.2×1013 cm-2. Changes in both DC leakage current and small-signal circuit components are examined. Degradation in performance due to total-ionizing dose is shown to be suppressed by non-quasi-static effects during RF operation. Tolerance to displacement damage from fast neutrons is also observed, which is explained using TCAD simulations. Overall, the characterized pin diodes are tolerant to cumulative radiation at levels consistent with space applications such as geosynchronous weather satellites.
Global thinning of integrated circuits is a technique that enables backside failure analysis and radiation testing. Prior work also shows increased thresholds for single-event latchup and upset in thinned devices. We present impacts of global thinning on device performance and reliability of 28 nm node field programmable gate arrays (FPGA). Devices are thinned to values of 50, 10, and 3 microns using a micromachining and polishing method. Lattice damage, in the form of dislocations, extend about 1 micron below the machined surface. The damage layer is removed after polishing with colloidal SiO2 slurry. We create a 2D finite-element model with liner elasticity equations and flip-chip packaged device geometry to show that thinning increases compressive global stress in the Si, while C4 bumps increase stress locally. Measurements of stress using Raman spectroscopy qualitatively agree with our stress model but also reveal the need for more complex structural models to account for nonlinear effects occurring in devices thinned to 3 microns and after temperature cycling to 125 °C. Thermal imaging shows that increased local heating occurs with increased thinning but the maximum temperature difference across the 3-micron die is less than 2 °C. Ring oscillators (ROs) programmed throughout the FPGA fabric slow about 0.5% after thinning compared to full thickness values. Temperature cycling the devices to 125 °C further decreases RO frequency about 0.5%, which we attribute to stress changes in the Si.
The performance of Nuclear Deterrence (ND) systems could be improved by adopting advanced commercial CMOS technologies. However, the radiation hardness of these ND systems must be assured. This project quantified dose rate upset thresholds, allowing us to evaluate whether advanced commercial technologies can be used in rad hard applications. This project also evaluated the susceptibility of advanced commercial technologies to neutron displacement damage and single event effects, and developed hardness assurance methods. As a result of this work, Sandia is now collaborating more closely with DoD agencies and their contractors to understand and improve the radiation hardness of advanced commercial technologies. Sandia Capabilities (SPHINX, lon Beam Lab, FPGA test capabilities) were developed and are being utilized by other programs. Staff were trained to do radiation survivability testing and developed proposals that were funded. Internal and external collaborations and partnerships were developed, including with Georgia Tech. This project received the Best Paper award at the 2019 Hardened Electronics And Radiation Technology (HEART) Conference.
The effects of 14-MeV neutron displacement damage (DD) on waveguide (WG)-integrated germanium-on-silicon p-i-n photodiodes (PDs) for silicon photonics have been investigated up to the fluences of 7.5× 1012 n/cm2 (14 MeV) or 1.4× 1013 n1-MeVeq/cm2(Si). This article includes the measurements of dark current-voltage characteristics across temperature from 150 to 375 K, measurements of PD junction capacitance, spectral response measurements from 1260 to 1360 nm, and frequency-response measurements. The devices are found to be susceptible to DD-induced carrier removal effects; however, they also continue to operate without meaningful impact to performance for the DD dose levels examined. Since the PD test chips include silicon photonic integrated grating couplers and WGs, which carry the optical signal to the PD, some assessment of the impact of DD on these passive devices can also be inferred. This article does not examine the short-term annealing or transient behavior of the DD, and instead, it has only considered the lasting damage that remains after any initial period of room-temperature annealing.
Wang, Peng; Sternberg, Andrew L.; Sierawski, Brian D.; Zhang, En X.; Tonigan, A.M.; Brewer, Rachel M.; Dodds, Nathaniel A.; Vizkelethy, Gyorgy V.; Jordan, Scott L.; Fleetwood, Daniel M.; Reed, Robert A.; Schrimpf, Ronald D.
Wang, Peng; Sternberg, Andrew L.; Kozub, John A.; Zhang, En X.; Dodds, Nathaniel A.; Jordan, Scott L.; Fleetwood, Daniel M.; Reed, Robert A.; Schrimpf, Ronald D.
Two-photon absorption (TPA) pulsed-laser testing is used to analyze the TPA-induced single-event latchup sensitive-area of a specially designed test structure. This method takes into account the existence of an onset region in which the probability of triggering latchup transits between 0 and 1 as the laser pulse energy increases. This variability is attributed to a combination of laser pulse-to-pulse variability and variations in local carrier density and temperature. For each spatial position, the latchup probability associated with a given energy is calculated. Calculation of latchup cross section at lower laser energies, relative to onset, is improved significantly by taking into account the full probability distribution. The transition from low probability of latchup to high probability is more abrupt near the source contacts than for surrounding areas.
We discuss upsets in erased floating gate cells, due to large threshold voltage shifts, using statistical distributions collected on a large number of memory cells. The spread in the neutral threshold voltage appears to be too low to quantitatively explain the experimental observations in terms of simple charge loss, at least in SLC devices. The possibility that memories exposed to high energy protons and heavy ions exhibit negative charge transfer between programmed and erased cells is investigated, although the analysis does not provide conclusive support to this hypothesis.
We present low-energy proton single-event upset (SEU) data on a 65 nm SOI SRAM whose substrate has been completely removed. Since the protons only had to penetrate a very thin buried oxide layer, these measurements were affected by far less energy loss, energy straggle, flux attrition, and angular scattering than previous datasets. The minimization of these common sources of experimental interference allows more direct interpretation of the data and deeper insight into SEU mechanisms. The results show a strong angular dependence, demonstrate that energy straggle, flux attrition, and angular scattering affect the measured SEU cross sections, and prove that proton direct ionization is the dominant mechanism for low-energy proton-induced SEUs in these circuits.
Khachatrian, Ani; Roche, Nicolas J.H.; Dodds, Nathaniel A.; Mcmorrow, Dale; Warner, Jeffrey H.; Buchner, Stephen P.; Reed, Robert A.
Charge-collection experiments and simulations designed to quantify the effects of reflections from metallization during through-wafer TPA testing are presented. The results reveal a strong dependence on metal line width and metal line position inside the {rm SiO}2 overlayer. The charge-collection enhancement is largest for the widest metal lines and the metal lines closest to the {rm Si}/{rm SiO}2 interface. The charge-collection enhancement is also dependent on incident laser pulse energy, an effect that is a consequence of higher-order optical nonlinearities induced by the ultrashort optical pulses. However, for the lines further away from the {rm Si}/{rm SiO}2 interface, variations in laser pulse energies affect the charge-collection enhancement to a lesser degree. Z-scan measurements reveal that the peak charge collection occurs when the axial position of the laser focal point is inside the Si substrate. There is a downward trend in peak collected-charge enhancement with the increase in laser pulse energies for the metal lines further away from the {rm Si}/{rm SiO}2 interface. Metallization enhances the collected charge by same amount regardless of the applied bias voltage. For thinner metal lines and laser pulse energies lower than 1 nJ, the collected charge enhancement due to metallization is negligible.
Low-and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.
Low-and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.
Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. As a result, grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.
This report briefly summarizes three publications that resulted from a two-year LDRD. The three publications address a recently emerging reliability issue: namely, that low-energy protons (LEPs) can cause single-event effects (SEEs) in highly scaled microelectronics. These publications span from low to high technology readiness levels. In the first, novel experiments were used to prove that proton direct ionization is the dominant mechanism for LEP-induced SEEs. In the second, a simple method was developed to calculate expected on-orbit error rates for LEP effects. This simplification was enabled by creating (and characterizing) an accelerated space-like LEP environment in the laboratory. In the third publication, this new method was applied to many memory circuits from the 20-90 nm technology nodes to study the general importance of LEP effects, in terms of their contribution to the total on-orbit SEE rate.
The recipients of the 2014 NSREC Outstanding Conference Paper Award are Nathaniel A. Dodds, James R. Schwank, Marty R. Shaneyfelt, Paul E. Dodd, Barney L. Doyle, Michael Trinczek, Ewart W. Blackmore, Kenneth P. Rodbell, Michael S. Gordon, Robert A. Reed, Jonathan A. Pellish, Kenneth A. LaBel, Paul W. Marshall, Scot E. Swanson, Gyorgy Vizkelethy, Stuart Van Deusen, Frederick W. Sexton, and M. John Martinez, for their paper entitled "Hardness Assurance for Proton Direct Ionization-Induced SEEs Using a High-Energy Proton Beam." For older CMOS technologies, protons could only cause single-event effects (SEEs) through nuclear interactions. Numerous recent studies on 90 nm and newer CMOS technologies have shown that protons can also cause SEEs through direct ionization. Furthermore, this paper develops and demonstrates an accurate and practical method for predicting the error rate caused by proton direct ionization (PDI).