Seebeck Enhancement via Quantum Confinement in MOSFET's: Towards Monolithic On-Chip Cooling
Abstract not provided.
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Jump to search filtersSingle-Event Upsets and Distributions in Radiation-Hardened CMOS Flip-Flop Logic Chains
IEEE Transactions on Nuclear Science
Abstract not provided.
Single-Event Upsets and Distributions in Radiation-Hardened CMOS Flip-Flop Logic Chains
Abstract not provided.
Effects of moisture on radiation-induced degradation in CMOS SOI transistors
Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS
The effects of moisture on radiation-induced charge buildup in the oxides of a 0.35 m SOI technology are explored. Data show no observable effects of moisture-related aging on radiation hardness. These results are in contrast to those of previous work performed on bulk MOS technologies fabricated in the 1980s. The cause of these differences do not appear to be due to differences in final chip passivation layers. Instead, other processing variables (including the use of different implant materials and thicker overlayers) may account for these differences. In any case, the SOI technology results indicate that not all advanced technologies exposed to moisture are necessarily susceptible to significant long-term radiation-induced aging effects. © 2009 IEEE.
High Speed (Ghz) Ultra-high pressure (GPa) Sensor array fabricated in Integrated CMOS+MEMS process
Abstract not provided.
Transmission electron microscopy and scanning capacitance microscopy analysis of dislocation-induced leakages in n-channel I/O transistors
Abstract not provided.
Transmission Electron Microscopy and Scanning Capacitance Microscopy Analysis of Dislocation-Induced Leakages in n-channel I/O Transistors
Proposed for publication in the Conference proceedings from the 31st International Symposium for Testing and Failure Analysis.
Abstract not provided.
Novel application of transmission electron microscopy and scanning capacitance microscopy for defect root cause identification and yield enhancement
Abstract not provided.
Identification of radiation-induced parasitic leakage paths using light emission microscopy
Abstract not provided.
Application of the modified voltage-dividing potentiometer to overlay metrology in a CMOS/bulk process
The measurement of layer-to-layer feature overlay will, in the foreseeable future, continue to be a critical metrological requirement for the semiconductor industry. Meeting the image placement metrology demands of accuracy, precision, and measurement speed favors the use of electrical test structures. In this paper, a two-dimensional, modified voltage-dividing potentiometer is applied to a short-loop VLSI process to measure image placement. The contributions of feature placement on the reticle and overlay on the wafer to the overall measurement are analyzed and separated. Additional sources of uncertainty are identified, and methods developed to monitor and reduce them are described.
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