This work shows that the static random access memory (SRAM) error rate for a commercial 65-nm device in a dose rate environment can be highly dependent upon the integrated dose (dose rate × pulse duration). While the typical metric for such testing is dose rate upset (DRU) level in rad(Si)/s, a series of dose rate experiments at Little Mountain Test Facility (LMTF) shows dependence on the integrated dose. The error rate is also found to be dependent on the core voltage, and the preradiation value of the bits. We believe that these effects are explained by a well charge depletion caused by gamma ray photocurrent.
TinMan is the first technology to continuously measure thermal neutron intensity during aircraft flight and to define this environment, an important achievement since changes to semiconductors have led electronic parts to become more sensitive to thermal nuetrons that may lead to disturbances in their operation.
Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor's scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Thus, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop's sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.
Semiconductor-insulator interfaces play an important role in the reliability of integrated devices; however, the impact of these interfaces on the physical mechanisms related to single-event effects has not been previously reported. We present experimental data that demonstrate that single-event charge collection can be impacted by changes in interface quality. The experimental data, combined with simulations, show that single-event response may depend on surface recombination at interface defects. The effect depends on strike location and increases with increasing linear energy transfer (LET). Surface recombination can affect single-event charge collection for interfaces with a surface recombination velocity (SRV) of 1000 cm/s and is a dominant charge collection mechanism with SRV > 10^{5} cm/s.
Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories' CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.
King, Michael P.; Ryder, Kaitlyn L.; Ryder, Landen D.; Sternberg, Andrew L.; Kozub, John A.; Zhang, En X.; Khachatrian, Ani; Buchner, Steven P.; Mcmorrow, Dale P.; Hales, Joel M.; Zhao, Yuanfu; Wang, Liang; Wang, Chuanmin; Weller, Robert A.; Schrimpf, Ronald D.; Weiss, Sharon M.; Reed, Robert A.; Black, Dolores A.
A sensitive volume is developed using pulsed laser-induced collected charge for two bias conditions in an epitaxial silicon diode. These sensitive volumes show good agreement with experimental two photon absorption laser-induced collected charge at a variety of focal positions and pulse energies. When compared to ion-induced collected charge, the laser-based sensitive volume over predicts the experimental collected charge at low bias and agrees at high bias. Here, a sensitive volume based on ion-induced collected charge adequately describes the ion experimental results at both biases. Differences in the amount of potential modulation explain the differences between the ion-and laser-based sensitive volumes at the lower bias. Truncation of potential modulation by the highly doped substrate at the higher bias results in similar sensitive volumes.
Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.
Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.
The effect of a linear accelerator's (LINAC's) microstructure (i.e., train of narrow pulses) on devices and the associated transient photocurrent models are investigated. The data indicate that the photocurrent response of Si-based RF bipolar junction transistors and RF p-i-n diodes is considerably higher when taking into account the microstructure effects. Similarly, the response of diamond, SiO2, and GaAs photoconductive detectors (standard radiation diagnostics) is higher when taking into account the microstructure. This has obvious hardness assurance implications when assessing the transient response of devices because the measured photocurrent and dose rate levels could be underestimated if microstructure effects are not captured. Indeed, the rate the energy is deposited in a material during the microstructure peaks is much higher than the filtered rate which is traditionally measured. In addition, photocurrent models developed with filtered LINAC data may be inherently inaccurate if a device is able to respond to the microstructure.
Here, the effect of a linear accelerator’s (LINAC’s) microstructure (i.e., train of narrow pulses) on devices and the associated transient photocurrent models are investigated. The data indicate that the photocurrent response of Si-based RF bipolar junction transistors and RF p-i-n diodes is considerably higher when taking into account the microstructure effects. Similarly, the response of diamond, SiO2, and GaAs photoconductive detectors (standard radiation diagnostics) is higher when taking into account the microstructure. This has obvious hardness assurance implications when assessing the transient response of devices because the measured photocurrent and dose rate levels could be underestimated if microstructure effects are not captured. Indeed, the rate the energy is deposited in a material during the microstructure peaks is much higher than the filtered rate which is traditionally measured. In addition, photocurrent models developed with filtered LINAC data may be inherently inaccurate if a device is able to respond to the microstructure.
Single event effects (SEE) are a reliability concern for modern microelectronics. Bit corruptions can be caused by single event upsets (SEUs) in the storage cells or by sampling single event transients (SETs) from a logic path. An accurate prediction of soft error susceptibility from SETs requires good models to convert collected charge into compact descriptions of the current injection process. This paper describes a simple, yet effective, method to model the current waveform resulting from a charge collection event for SET circuit simulations. The model uses two double-exponential current sources in parallel, and the results illustrate why a conventional model based on one double-exponential source can be incomplete. A small set of logic cells with varying input conditions, drive strength, and output loading are simulated to extract the parameters for the dual double-exponential current sources. The parameters are based upon both the node capacitance and the restoring current (i.e., drive strength) of the logic cell.