Publications

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Electrostatic discharge (ESD) and electrical overstress (EOS) damage of Micro-Electro-Mechanical Systems (MEMS) has been identified as a new failure mode. This failure mode has not been previously recognized or addressed primarily due to the mechanical nature and functionality of these systems, as well as the physical failure signature that resembles stiction. Because many MEMS devices function by electrostatic actuation, the possibility of these devices not only being susceptible to ESD or EOS damage but also having a high probability of suffering catastrophic failure due to ESD or EOS is very real. Results from previous experiments have shown stationary comb fingers adhered to the ground plane on MEMS devices tested in shock, vibration, and benign environments. Using Sandia polysilicon microengines, we have conducted tests to establish and explain the ESD/EOS failure mechanism of MEMS devices. These devices were electronically and optically inspected prior to and after ESD and EOS testing. This paper will address the issues surrounding MEMS susceptibility to ESD and EOS damage as well as describe the experimental method and results found from ESD and EOS testing. The tests were conducted using conventional IC failure analysis and reliability assessment characterization tools. In this paper we will also present a thermal model to accurately depict the heat exchange between an electrostatic comb finger and the ground plane during an ESD event.

Commercial focused ion beam (FIB) systems are commonly used to image integrated circuits (ICS) after device processing, especially in failure analysis applications. FIB systems are also often employed to repair faults in metal lines for otherwise functioning ICS, and are being evaluated for applications in film deposition and nanofabrication. A problem that is often seen in FIB imaging and repair is that ICS can be damaged during the exposure process. This can result in degraded response or out-right circuit failure. Because FIB processes typically require the surface of an IC to be exposed to an intense beam of 30--50 keV Ga{sup +} ions, both charging and secondary radiation damage are potential concerns. In previous studies, both types of effects have been suggested as possible causes of device degradation, depending on the type of device examined and/or the bias conditions. Understanding the causes of this damage is important for ICS that are imaged or repaired by a FIB between manufacture and operation, since the performance and reliability of a given IC is otherwise at risk in subsequent system application. In this summary, the authors discuss the relative roles of radiation damage and charging effects during FIB imaging. Data from exposures of packaged parts under controlled bias indicate the possibility for secondary radiation damage during FIB exposure. On the other hand, FIB exposure of unbiased wafers (a more common application) typically results in damage caused by high-voltage stress or electrostatic discharge. Implications for FIB exposure and subsequent IC use are discussed.

Sandia is manufacturing CMOS ICs with 0.5 {micro}m LOCOS and shallow trench isolation (STI) technologies and is developing a 0.35 {micro}m SOI technology. A program based on burn-in and life tests is being used to qualify the 0.5 {micro}m technologies for delivery of high reliability ICs to customers for military and space applications. Representative ICs from baseline wafer lots are assembled using a high reliability process with multilayer hermetic, ceramic packages. These ICs are electrically tested before, during, and after burn-in and subsequent 1000 hour dynamic and static life tests. Two types of ICS are being used for this qualification, a 256K bit SRAM and a Microcontroller Core (MCC). Over 600 ICs have successfully completed these qualification tests, resulting in a failure rate estimate of less than 4 FITS for satellite applications. Recently, a group of SRAMS from a development wafer lot incorporating nonqualified processes of the 0.5 {micro}m LOCOS technology had an unusually high number of failures during the initial electrical test after packaging. The investigation of these failures is described.

I{sub DDQ} testing of CMOSICs is a technique for production quality and reliability improvement, design validation, and failure analysis. The origin and basic concepts of I{sub DDQ} testing are reviewed. The relationship of I{sub DDQ} testing to other test methods is considered in the context of the whole IC life cycle from design, fabrication, and test through end use. A comprehensive test strategy is described that uses defect classes based on defect electrical properties rather than traditional fault models.

The IC test industry has struggled for more than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the test strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and test facilities and from public literature. We describe test pattern requirements for each defect class and propose a test paradigm.

Degradation in nMOS transistors from gate oxide shorts is dependent upon oxide trapping and interface state generation. Three distinct damage mechanisms were identified, including generation of: (1) electron traps in the bulk oxide by the injected holes, N{sub ox,h}, (2) electron traps in the bulk oxide by the injected electrons, N{sub ox,e}, and (3) interface states, N{sub ss}. The three damage mechanisms are incorporated into a device lifetime prediction method.

I{sub DDQ} testing is mandatory to ensure that low power CMOS ICs meet their design intent. I{sub DDQ} testing is both a design verifier for low quiescent current and a sensitive production test for defects. Quiescent power reduction is particularly important for products such as cardiac pacemakers, laptop computers, and cellular telephones.

Significant improvements in CMOSIC quality, reliability, and fabrication yield can be readily achieved in the 1990s by appropriate implementation of tests for quiescent power supply current (I{sub DDQ}). As part of an overall quality management program, I{sub DDQ} testing incorporated with design for testability and modified conventional logic response testing enables 100% stuck-at fault coverage, quality improvement goals of defective levels less than 100 PPM, and reliability greater than 0.999 for 30 years. 9 refs., 2 figs., 1 tab.

Simplified ATPG and fault simulation algorithms, reduced test set sizes, and increased fault coverage are achieved with I {sub DDQ} testing for stuck-at faults. In addition, I {sub DDQ} testing will detect logically redundant and multiple stuck-at faults, and improve the detection of non-stuck-at fault defects. 17 refs., 6 figs., 6 tabs.