3D integration of multiple microelectronic devices improves size, weight, and power while increasing the number of interconnections between components. One integration method involves the use of metal bump bonds to connect devices and components on a common interposer platform. Significant variations in the coefficient of thermal expansion in such systems lead to stresses that can cause thermomechanical and electrical failures. More advanced characterization and failure analysis techniques are necessary to assess the bond quality between components. Frequency domain thermoreflectance (FDTR) is a nondestructive, noncontact testing method used to determine thermal properties in a sample by fitting the phase lag between an applied heat flux and the surface temperature response. The typical use of FDTR data involves fitting for thermal properties in geometries with a high degree of symmetry. In this work, finite element method simulations are performed using high performance computing codes to facilitate the modeling of samples with arbitrary geometric complexity. A gradient-based optimization technique is also presented to determine unknown thermal properties in a discretized domain. Using experimental FDTR data from a GaN-diamond sample, thermal conductivity is then determined in an unknown layer to provide a spatial map of bond quality at various points in the sample.
IEEE Transactions on Components, Packaging and Manufacturing Technology
Jia, Xiaofan; Li, Xingchen; Erdogan, Serhat; Moon, Kyoung S.; Kim, Joon W.; Jordan, Matthew J.; Swaminathan, Madhavan
This article presents the antenna-integrated glass interposer for $D$ -band 6G wireless applications using die-embedding technology. We implement the die-embedded package on glass substrates and characterize the electrical performance in the $D$ -band. The electrical characterization employs embedded test dies with the 50- $\Omega $ ground-signal-ground (GSG) ports and coplanar waveguides. We achieve low-loss die-to-package transitions by using staggered dielectric vias, which are compared with the transitions of wire-bonding and flip-chip assembly. This article provides detailed information on the design, modeling, fabrication, and characterization of the die-to-package interconnects. This article also demonstrates the integration of microstrip patch antenna array and embedded dies in the $D$ -band. The results show superior electrical performance provided by the die-embedded glass interposer. The die-to-package interconnect exhibits good matching (less than -10-dB S11) and low loss (0.2-dB loss) in the $D$ -band. The integrated $1\times8$ patch antenna array shows 11.6-dB broadside gain and good matching with the embedded die. In addition, by using a temporary carrier, the antenna-integrated glass interposer also has great potential for further heterogeneous integration and thermal management.
Proceedings - Electronic Components and Technology Conference
Li, Xingchen; Jia, Xiaofan; Kim, Joon W.; Moon, Kyoung S.; Jordan, Matthew J.; Swaminathan, Madhavan
This paper presents a die-embedded glass interposer with minimum warpage for 5G/6G applications. The interposer performs high integration with low-loss interconnects by embedding multiple chips in the same glass substrate and interconnecting the chips through redistributive layers (RDL). Novel processes for cavity creation, multi-die embedding, carrier- less RDL build up and heat spreader attachment are proposed and demonstrated in this work. Performance of the interposer from 1 GHz to 110 GHz are evaluated. This work provides an advanced packaging solution for low-loss die-to-die and die-to-package interconnects, which is essential to high performance wireless system integration.
CTE (coefficient of thermal expansion) mismatch between two wafers has potential for brittle failure when large areas are bonded on top of one another (wafer to wafer or wafer to die bonds). To address this type of failure, we proposed patterning a polymer around metallic interconnects. For this project, utilized benzo cyclobutene (BCB) to form the bond and accommodate stress. For the metal interconnects, we used indium. To determine the benefits of utilizing BCB, mechanical shear testing of die bonding with just BCB were compared to die bonded just with oxide. These tests demonstrated that BCB, when cured for only 30 minutes and bonded at 200°C, the BCB was able to withstand shear forces similar to oxide. Furthermore, when the BCB did fail, it experienced a more ductile failure, allowing the silicon to crack, rather than shatter. To demonstrate the feasibility of using BCB between indium interconnects, wafers were pattered with layers of BCB with vias for indium or ENEPIG (electroless nickel, electroless palladium, immersion gold). Subsequently, these wafers were pattered with a variety of indium or ENEPIG interconnect pitches, diameters, and heights. These dies were bonded under a variety of conditions, and those that held a bond, were cross-sectioned and imaged. Images revealed that certain bonding conditions allow for interconnects and BCB to achieve a void-less bond and thus demonstrate that utilizing polymers in place of oxide is a feasible way to reduce CTE stress.
Proceedings - Electronic Components and Technology Conference
Jia, Xiaofan; Moon, Kyoung S.; Kim, Joon W.; Huang, Kai Q.; Jordan, Matthew J.; Swaminathan, Madhavan
This work presents the implementation and characterization of a die-embedded, antenna-integrated glass package for RF modules in D-Band. The proposed package uses glass as the core material which can match the coefficient-of-thermal-expansion (CTE) well for RF chips and printed circuit board (PCB). The redistribution layer (RDL) for electrical connections is built on low-loss polymeric build-up dielectric films (ABF-GL102). Dummy dies are embedded in the glass cavities for characterization. The interconnects between die pads and the package are implemented using micro-vias. An 8-elements series-fed microstrip patch antenna is also integrated on the low-loss RDL. The proposed glass panel embedded package addresses the electrical loss and parasitic from the interconnects. With micro-vias and transmission lines built on low-loss RDL, the glass embedded package provides low-loss and low-parasitic chip-to-chip and chip-to-antenna interconnects. Using temporary thermal release tapes, this package also shows great potential to address the high heat dissipation from D-band power amplifiers.
Plasmas formed in microscale gaps at DC and plasmas formed at radiofrequency (RF) both deviate in behavior compared to the classical Paschen curve, requiring lower voltage to achieve breakdown due to unique processes and dynamics, such as field emission and controlled rates of electron/ion interactions. Both regimes have been investigated independently, using high precision electrode positioning systems for microscale gaps or large, bulky emitters for RF. However, no comprehensive study of the synergistic phenomenon between the two exists. The behavior in such a combined system has the potential to reach sub-10 V breakdown, which combined with the unique electrical properties of microscale plasmas could enable a new class of RF switches, limiters and tuners.This work describes the design and fabrication of novel on-wafer microplasma devices with gaps as small as 100 nm to be operated at GHz frequencies. We used a dual-sacrificial layer process to create devices with microplasma gaps integrated into RF compatible 50 Ω coplanar waveguide transmission lines, which will allow this coupled behaviour to be studied for the first time. These devices are modelled using conventional RF simulations as well as the Sandia code, EMPIRE, which is capable of modelling the breakdown and formation of plasma in microscale gaps driven by high frequencies. Synchronous evaluation of the modelled electrical and breakdown behaviour is used to define device structures, predict behaviour and corroborate results. We further report preliminary independent testing of the microscale gap and RF behaviour. DC testing shows modified-Paschen curve behaviour for plasma gaps at and below four microns, demonstrating decreased breakdown voltage with reduced gap size. Additionally, preliminary S-parameter measurements of as-prepared and connectorized devices have elucidated RF device behaviour. Together, these results provide baseline data that enables future experiments as well as discussion of projected performance and applications for these unique devices.