Non-invasive imaging of microwave (MW) magnetic fields with microscale lateral resolution is pivotal for various applications, such as MW technologies and integrated circuit failure analysis. Diamond nitrogen-vacancy (NV) center magnetometry has emerged as an ideal tool, offering micrometer-scale resolution, millimeter-scale field of view, high sensitivity, and non-invasive imaging compatible with diverse samples. However, up until now, it has been predominantly used for imaging of static or low-frequency magnetic fields or, concerning MW field imaging, to directly characterize the same microwave device used to drive the NV spin transitions. In this work, we leverage an NV center ensemble in diamond for wide-field imaging of MW magnetic fields generated by a test device employing a differential measurement protocol. The microscope is equipped with a MW loop to induce Rabi oscillations between NV spin states, and the MW field from the device-under-test is measured through local deviations in the Rabi frequency. This differential protocol yields magnetic field maps of a 2.57 GHz MW field with a sensitivity of ∼ 9 μ T Hz− 1/2 for a total measurement duration of T = 357 s, covering a 340 × 340 μ m2 field of view with a micrometer-scale spatial resolution and a device-under-test input power dynamic range of 30 dB. This work demonstrates a novel NV magnetometry protocol, based on differential Rabi frequency measurement, that extends NV wide-field imaging capabilities to imaging of weak MW magnetic fields that would be difficult to measure directly through standard NV Rabi magnetometry.
In this study, we address the challenge of enhancing image quality and spatial resolution in computed tomography (CT) imaging by introducing simulation and fabrication of high aspect ratio, point-like transmission targets. Utilizing advanced electroplating techniques, traditionally employed in the fabrication of Through Substrate Via (TSV) interconnects for CMOS circuitry, we successfully embed copper targets within silicon substrates. This method allows us to create high-aspect-ratio features specifically designed for X-ray transmission targets, resulting in micro targets that exhibit a volume increase compared to conventional evaporated surface targets. Furthermore, we present simulation results of the X-ray spectrum generated by these targets, demonstrating their potential to significantly improve both image quality and spatial resolution in CT applications. Our findings suggest that leveraging advanced fabrication techniques can open new avenues for the development of enhanced imaging technologies in medical diagnostics and beyond.
Surface ion traps are a promising platform for quantum computing due to their potential to store large numbers of ions that can be addressed by electrical and optical control signals in order to implement quantum algorithms. Increasing the power of the quantum computer requires increasing the number of ions, but this poses a significant challenge in that it leads to a non-linear increase in on-chip power dissipation. The primary contributor to this power scaling in current devices is the capacitance between the radio frequency (RF) electrode and the metal plane that shields the silicon substrate from the RF signals applied to it. Silicon has traditionally been chosen for the substrate material for compatibility with the processing required for multi-metal-level traps. In this work, we address these capacitance and fabrication challenges by replacing the commonly used silicon substrate with an insulating sapphire substrate to fabricate a multi-metal-level ion trap, while still employing common semiconductor manufacturing techniques. This change in substrate allows the design to remove the metal shielding from the device design, reducing the capacitance of the RF electrode. The electrical characteristics of these traps were measured, specifically trap impedance, capacitance, and voltage breakdown, and compared to nearly identical silicon trap devices. Finally, we used laser cutting techniques to shape a sapphire wafer into bowtie shapes matching silicon traps previously fabricated at Sandia National Labs to explore solutions for integrating sapphire substrates into non-rectangular ion trap designs.
Low-dimensional materials show great promise for enhanced computing and sensing performance in mission-relevant environments. However, integrating low-dimensional materials into conventional electronics remains a challenge. Here, we demonstrate a novel transfer method by which low-dimensional materials and their heterostructures can be transferred onto any arbitrary substrate. Our method relies on a water soluble GeO2 substrate from which lowdimensional materials are transferred without significant perturbation. We apply the method to transfer a working electronic device based on a low-dimensional material. Process developments are achieved to enable the fabrication and transfer of a working electronic device, including the growth of high-k dielectric on GeO2 by atomic layer deposition and inserting an indium diffusion barrier into the device gate stack. This work supports Sandia’s heterogeneous integration strategy to broaden the implementation of low-dimensional films and their devices.
3D integration of multiple microelectronic devices improves size, weight, and power while increasing the number of interconnections between components. One integration method involves the use of metal bump bonds to connect devices and components on a common interposer platform. Significant variations in the coefficient of thermal expansion in such systems lead to stresses that can cause thermomechanical and electrical failures. More advanced characterization and failure analysis techniques are necessary to assess the bond quality between components. Frequency domain thermoreflectance (FDTR) is a nondestructive, noncontact testing method used to determine thermal properties in a sample by fitting the phase lag between an applied heat flux and the surface temperature response. The typical use of FDTR data involves fitting for thermal properties in geometries with a high degree of symmetry. In this work, finite element method simulations are performed using high performance computing codes to facilitate the modeling of samples with arbitrary geometric complexity. A gradient-based optimization technique is also presented to determine unknown thermal properties in a discretized domain. Using experimental FDTR data from a GaN-diamond sample, thermal conductivity is then determined in an unknown layer to provide a spatial map of bond quality at various points in the sample.
IEEE Transactions on Components, Packaging and Manufacturing Technology
Jia, Xiaofan; Li, Xingchen; Erdogan, Serhat; Moon, Kyoung S.; Kim, Joon W.; Jordan, Matthew B.; Swaminathan, Madhavan
This article presents the antenna-integrated glass interposer for $D$ -band 6G wireless applications using die-embedding technology. We implement the die-embedded package on glass substrates and characterize the electrical performance in the $D$ -band. The electrical characterization employs embedded test dies with the 50- $\Omega $ ground-signal-ground (GSG) ports and coplanar waveguides. We achieve low-loss die-to-package transitions by using staggered dielectric vias, which are compared with the transitions of wire-bonding and flip-chip assembly. This article provides detailed information on the design, modeling, fabrication, and characterization of the die-to-package interconnects. This article also demonstrates the integration of microstrip patch antenna array and embedded dies in the $D$ -band. The results show superior electrical performance provided by the die-embedded glass interposer. The die-to-package interconnect exhibits good matching (less than -10-dB S11) and low loss (0.2-dB loss) in the $D$ -band. The integrated $1\times8$ patch antenna array shows 11.6-dB broadside gain and good matching with the embedded die. In addition, by using a temporary carrier, the antenna-integrated glass interposer also has great potential for further heterogeneous integration and thermal management.
Proceedings - Electronic Components and Technology Conference
Li, Xingchen; Jia, Xiaofan; Kim, Joon W.; Moon, Kyoung S.; Jordan, Matthew B.; Swaminathan, Madhavan
This paper presents a die-embedded glass interposer with minimum warpage for 5G/6G applications. The interposer performs high integration with low-loss interconnects by embedding multiple chips in the same glass substrate and interconnecting the chips through redistributive layers (RDL). Novel processes for cavity creation, multi-die embedding, carrier- less RDL build up and heat spreader attachment are proposed and demonstrated in this work. Performance of the interposer from 1 GHz to 110 GHz are evaluated. This work provides an advanced packaging solution for low-loss die-to-die and die-to-package interconnects, which is essential to high performance wireless system integration.
CTE (coefficient of thermal expansion) mismatch between two wafers has potential for brittle failure when large areas are bonded on top of one another (wafer to wafer or wafer to die bonds). To address this type of failure, we proposed patterning a polymer around metallic interconnects. For this project, utilized benzo cyclobutene (BCB) to form the bond and accommodate stress. For the metal interconnects, we used indium. To determine the benefits of utilizing BCB, mechanical shear testing of die bonding with just BCB were compared to die bonded just with oxide. These tests demonstrated that BCB, when cured for only 30 minutes and bonded at 200°C, the BCB was able to withstand shear forces similar to oxide. Furthermore, when the BCB did fail, it experienced a more ductile failure, allowing the silicon to crack, rather than shatter. To demonstrate the feasibility of using BCB between indium interconnects, wafers were pattered with layers of BCB with vias for indium or ENEPIG (electroless nickel, electroless palladium, immersion gold). Subsequently, these wafers were pattered with a variety of indium or ENEPIG interconnect pitches, diameters, and heights. These dies were bonded under a variety of conditions, and those that held a bond, were cross-sectioned and imaged. Images revealed that certain bonding conditions allow for interconnects and BCB to achieve a void-less bond and thus demonstrate that utilizing polymers in place of oxide is a feasible way to reduce CTE stress.
