Granular metals (GMs), consisting of metal nanoparticles separated by an insulating matrix, frequently serve as a platform for fundamental electron transport studies. However, few technologically mature devices incorporating GMs have been realized, in large part because intrinsic defects (e.g., electron trapping sites and metal/insulator interfacial defects) frequently impede electron transport, particularly in GMs that do not contain noble metals. Here, we demonstrate that such defects can be minimized in molybdenum-silicon nitride (Mo-SiNx) GMs via optimization of the sputter deposition atmosphere. For Mo-SiNx GMs deposited in a mixed Ar/N2 environment, x-ray photoemission spectroscopy shows a 40%-60% reduction of interfacial Mo-silicide defects compared to Mo-SiNx GMs sputtered in a pure Ar environment. Electron transport measurements confirm the reduced defect density; the dc conductivity improved (decreased) by 104-105 and the activation energy for variable-range hopping increased 10×. Since GMs are disordered materials, the GM nanostructure should, theoretically, support a universal power law (UPL) response; in practice, that response is generally overwhelmed by resistive (defective) transport. Here, the defect-minimized Mo-SiNx GMs display a superlinear UPL response, which we quantify as the ratio of the conductivity at 1 MHz to that at dc, Δ σ ω . Remarkably, these GMs display a Δ σ ω up to 107, a three-orders-of-magnitude improved response than previously reported for GMs. By enabling high-performance electric transport with a non-noble metal GM, this work represents an important step toward both new fundamental UPL research and scalable, mature GM device applications.
K-means clustering analysis is applied to frequency-domain thermoreflectance (FDTR) hyperspectral image data to rapidly screen the spatial distribution of thermophysical properties at material interfaces. Performing FDTR while raster scanning a sample consisting of 8.6 μ m of doped-silicon (Si) bonded to a doped-Si substrate identifies spatial variation in the subsurface bond quality. Routine thermal analysis at select pixels quantifies this variation in bond quality and allows assignment of bonded, partially bonded, and unbonded regions. Performing this same routine thermal analysis across the entire map, however, becomes too computationally demanding for rapid screening of bond quality. To address this, K-means clustering was used to reduce the dimensionality of the dataset from more than 20 000 pixel spectra to just K = 3 component spectra. The three component spectra were then used to express every pixel in the image through a least-squares minimized linear combination providing continuous interpolation between the components across spatially varying features, e.g., bonded to unbonded transition regions. Fitting the component spectra to the thermal model, thermal properties for each K cluster are extracted and then distributed according to the weighting established by the regressed linear combination. Thermophysical property maps are then constructed and capture significant variation in bond quality over 25 μ m length scales. The use of K-means clustering to achieve these thermal property maps results in a 74-fold speed improvement over explicit fitting of every pixel.
3D integration of multiple microelectronic devices improves size, weight, and power while increasing the number of interconnections between components. One integration method involves the use of metal bump bonds to connect devices and components on a common interposer platform. Significant variations in the coefficient of thermal expansion in such systems lead to stresses that can cause thermomechanical and electrical failures. More advanced characterization and failure analysis techniques are necessary to assess the bond quality between components. Frequency domain thermoreflectance (FDTR) is a nondestructive, noncontact testing method used to determine thermal properties in a sample by fitting the phase lag between an applied heat flux and the surface temperature response. The typical use of FDTR data involves fitting for thermal properties in geometries with a high degree of symmetry. In this work, finite element method simulations are performed using high performance computing codes to facilitate the modeling of samples with arbitrary geometric complexity. A gradient-based optimization technique is also presented to determine unknown thermal properties in a discretized domain. Using experimental FDTR data from a GaN-diamond sample, thermal conductivity is then determined in an unknown layer to provide a spatial map of bond quality at various points in the sample.
Characterizing interface trap states in commercial wide bandgap devices using frequency-based measurements requires unconventionally high probing frequencies to account for both fast and slow traps associated with wide bandgap materials. The C − ψ S technique has been suggested as a viable quasi-static method for determining the interface trap state densities in wide bandgap systems, but the results are shown to be susceptible to errors in the analysis procedure. This work explores the primary sources of errors present in the C − ψ S technique using an analytical model that describes the apparent response for wide bandgap MOS capacitor devices. Measurement noise is shown to greatly impact the linear fitting routine of the 1 / C S ∗ 2 vs ψ S plot to calibrate the additive constant in the surface potential/gate voltage relationship, and an inexact knowledge of the oxide capacitance is also shown to impede interface trap state analysis near the band edge. In addition, a slight nonlinearity that is typically present throughout the 1 / C S ∗ 2 vs ψ S plot hinders the accurate estimation of interface trap densities, which is demonstrated for a fabricated n-SiC MOS capacitor device. Methods are suggested to improve quasi-static analysis, including a novel method to determine an approximate integration constant without relying on a linear fitting routine.
This paper describes a process for forming a buried field shield in GaN by an etch-and-regrowth process, which is intended to protect the gate dielectric from high fields in the blocking state. GaN trench MOSFETs made at Sandia serve as the baseline to show the limitations in making a trench gated device without a method to protect the gate dielectric. Device data coupled with simulations show device failure at 30% of theoretical breakdown for devices made without a field shield. Implementation of a field shield reduces the simulated electric field in the dielectric to below 4 MV/cm at breakdown, which eliminates the requirement to derate the device in order to protect the dielectric. For realistic lithography tolerances, however, a shield-to-channel distance of 0.4 μm limits the field in the gate dielectric to 5 MV/cm and requires a small margin of device derating to safeguard a long-term reliability and lifetime of the dielectric.
Vertical gallium nitride (GaN) p-n diodes have garnered significant interest for use in power electronics where high-voltage blocking and high-power efficiency are of concern. In this article, we detail the growth and fabrication methods used to develop a large area (1 mm2) vertical GaN p-n diode capable of a 6.0-kV breakdown. We also demonstrate a large area diode with a forward pulsed current of 3.5 A, an 8.3-mΩ·cm2 differential specific ON-resistance, and a 5.3-kV reverse breakdown. In addition, we report on a smaller area diode (0.063 mm2) that is capable of 6.4-kV breakdown with a differential specific ON-resistance of 10.2 m·Ω·cm2, when accounting for current spreading through the drift region at a 45° angle. Finally, the demonstration of avalanche breakdown is shown for a 0.063-mm2 diode with a room temperature breakdown of 5.6 kV. These results were achieved via epitaxial growth of a 50-μm drift region with a very low carrier concentration of < 1×1015 cm-3 and a carefully designed four-zone junction termination extension.