Publications

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We report Pauli blockade in a multielectron silicon metal–oxide–semiconductor double quantum dot with an integrated charge sensor. The current is rectified up to a blockade energy of 0.18 ± 0.03 meV. The blockade energy is analogous to singlet–triplet splitting in a two electron double quantum dot. Built-in imbalances of tunnel rates in the MOS DQD obfuscate some edges of the bias triangles. A method to extract the bias triangles is described, and a numeric rate-equation simulation is used to understand the effect of tunneling imbalances and finite temperature on charge stability (honeycomb) diagram, in particular the identification of missing and shifting edges. A bound on relaxation time of the triplet-like state is also obtained from this measurement.

We present the Quantum Computer Aided Design (QCAD) simulator that targets modeling quantum devices, particularly silicon double quantum dots (DQDs) developed for quantum qubits. The simulator has three differentiating features: (i) its core contains nonlinear Poisson, effective mass Schrodinger, and Configuration Interaction solvers that have massively parallel capability for high simulation throughput, and can be run individually or combined self-consistently for 1D/2D/3D quantum devices; (ii) the core solvers show superior convergence even at near-zero-Kelvin temperatures, which is critical for modeling quantum computing devices; (iii) it couples with an optimization engine Dakota that enables optimization of gate voltages in DQDs for multiple desired targets. The Poisson solver includes MaxwellBoltzmann and Fermi-Dirac statistics, supports Dirichlet, Neumann, interface charge, and Robin boundary conditions, and includes the effect of dopant incomplete ionization. The solver has shown robust nonlinear convergence even in the milli-Kelvin temperature range, and has been extensively used to quickly obtain the semiclassical electrostatic potential in DQD devices. The self-consistent Schrodinger-Poisson solver has achieved robust and monotonic convergence behavior for 1D/2D/3D quantum devices at very low temperatures by using a predictor-correct iteration scheme. The QCAD simulator enables the calculation of dot-to-gate capacitances, and comparison with experiment and between solvers. It is observed that computed capacitances are in the right ballpark when compared to experiment, and quantum confinement increases capacitance when the number of electrons is fixed in a quantum dot. In addition, the coupling of QCAD with Dakota allows to rapidly identify which device layouts are more likely leading to few-electron quantum dots. Very efficient QCAD simulations on a large number of fabricated and proposed Si DQDs have made it possible to provide fast feedback for design comparison and optimization.

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Back-contacted, ultrathin (<10 μm), and submillimeter-sized solar cells made with microsystem tools are a new type of cell that has not been optimized for performance. The literature reports efficiencies up to 15% using thicknesses of 14 μm and cell sizes of 250 μm. In this paper, we present the design, conditions, and fabrication parameters necessary to optimize these devices. The optimization was performed using commercial simulation tools from the microsystems arena. A systematic variation of the different parameters that influence the performance of the cell was accomplished. The researched parameters were resistance, Shockley-Read-Hall (SRH) lifetime, contact separation, implant characteristics (size, dosage, energy, and ratio between the species), contact size, substrate thickness, surface recombination, and light concentration. The performance of the cell was measured with efficiency, open-circuit voltage, and short-circuit current. Among all the parameters investigated, surface recombination and SRH lifetime proved to be the most important. Through completing the simulations, an optimized concept solar cell design was introduced for two scenarios: high and low quality materials/passivation. Simulated efficiencies up to 23.4% (1 sun) and 26.7% (100 suns) were attained for 20-μm-thick devices. Copyright © 2012 John Wiley & Sons, Ltd. Back-contacted, ultrathin (<10 μm), and submillimeter-sized solar cells made with microsystem tools are a new type of cell that has not been optimized for performance. In this paper, we present the design conditions and fabrication parameters necessary to optimize these devices via simulations. Through completing the simulations, an optimized concept solar cell design was introduced for two scenarios: high and low quality materials/passivation. Simulated efficiencies up to 23.4% (1 sun) and 26.7% (100 suns) were attained for 20-μm-thick devices. Copyright © 2012 John Wiley & Sons, Ltd.

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We present the Quantum Computer Aided Design (QCAD) simulator that targets modeling quantum devices, particularly Si double quantum dots (DQDs) developed for quantum computing. The simulator core includes Poisson, Schrodinger, and Configuration Interaction solvers which can be run individually or combined self-consistently. The simulator is built upon Sandia-developed Trilinos and Albany components, and is interfaced with the Dakota optimization tool. It is being developed for seamless integration, high flexibility and throughput, and is intended to be open source. The QCAD tool has been used to simulate a large number of fabricated silicon DQDs and has provided fast feedback for design comparison and optimization.

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The first demonstration of a silicon microring modulator with both an integrated resistive heater and diode-based temperature sensor is shown. The temperature-sensor exhibits a linear response for more than an 85 °C external temperature range. ©2010 Optical Society of America.

A novel silicon microdisk modulator with "error-free" ∼3 femtojoule/bit modulation at 12.5Gbs has been demonstrated. Modulation with a 1 volt swing allows for compatibility with current and future digital logic CMOS electronics. ©2010 IEEE.

We present a 2 x 2 silicon thermo-optic switch with a switching power of only {approx}12.5 mW and a response time of 5.4 {micro}s with an extinction ratio of {approx}>20 dB across the C and L bands.

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We fabricated a split-gate defined point contact in a double gate enhancement mode Si-MOS device, and implanted Sb donor atoms using a self-aligned process. E-beam lithography in combination with a timed implant gives us excellent control over the placement of dopant atoms, and acts as a stepping stone to focused ion beam implantation of single donors. Our approach allows us considerable latitude in experimental design in-situ. We have identified two resonance conditions in the point contact conductance as a function of split gate voltage. Using tunneling spectroscopy, we probed their electronic structure as a function of temperature and magnetic field. We also determine the capacitive coupling between the resonant feature and several gates. Comparison between experimental values and extensive quasi-classical simulations constrain the location and energy of the resonant level. We discuss our results and how they may apply to resonant tunneling through a single donor.

We report low-temperature transport measurements of a silicon metal-oxide-semiconductor (MOS) double quantum dot (DQD). In contrast to previously reported measurements of DQD's in Si MOS structures, our device has a lateral gate geometry very similar to that used by Petta et al. to demonstrate coherent manipulation of single electron spins. This gate design provides a high degree of tunability, allowing for independent control over individual dot occupation and tunnel barriers, as well as the ability to use nearby constrictions to sense dot charge occupation. Comparison of experimentally extracted capacitances between the dot and nearby gates with electrostatic modeling demonstrates the presence of disorder and the ability to partially compensate for this disorder by adjustment of gate voltages. We experimentally show gate-controlled tuning of the interdot coupling over a wide range of energies, an important step towards potential quantum computing applications.

We have compared simulations using solutions of Poisson's equation to detailed capacitance measurements on a double quantum dot structure. We tabulate the results and show which cases show good agreement and which do not. The capacitance values are also compared to those calculated by a solution of Laplace's equation. Electron density is plotted and discussed. In order to understand relevant potential barriers we compare simulations at 50 Kelvin to simulations at 15 Kelvin. We show that the charge density does not differ greatly, but that the conduction band potential does. However, a method of estimating the potential at 0 Kelvin based on the charge distribution at 50 Kelvin is shown to be close to the potential at 15 Kelvin. This method was used to estimate potential barriers at 0 Kelvin in two quantum dot structures.

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Thin and small form factor cells have been researched lately by several research groups around the world due to possible lower assembly costs and reduced material consumption with higher efficiencies. Given the popularity of these devices, it is important to have detailed information about the behavior of these devices. Simulation of fabrication processes and device performance reveals some of the advantages and behavior of solar cells that are thin and small. Three main effects were studied: the effect of surface recombination on the optimum thickness, efficiency, and current density, the effect of contact distance on the efficiency for thin cells, and lastly the effect of surface recombination on the grams per Watt-peak. Results show that high efficiency can be obtained in thin devices if they are well-passivated and the distance between contacts is short. Furthermore, the ratio of grams per Watt-peak is greatly reduced as the device is thinned.

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The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

A new class of microphotonic-resonators, Adiabatic Resonant Microrings (ARMs), is introduced. The ARM resonator geometry enables heater elements to be formed within the resonator, simultaneously enabling record low-power (4.4μW/GHz) and record high-speed (1μs) thermal tuning. ©2009 Optical Society of America.

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We demonstrate the first high-speed second-order silicon microdisk bandpass switch. The switch, constructed of a pair of 3 {micro}m radii active microdisks possesses {approx}40GHz flat-top passbands, a 4.2THz free-spectral-range, and a 2.4ns switching time.

We demonstrate the first high-speed second-order silicon microdisk bandpass switch. The switch, constructed of a pair of 3μm radii active microdisks possesses ~40GHz flat-top passbands, a 4.2THz free-spectral-range, and a 2.4ns switching time. © 2008 Optical Society of America.

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Under conditions that were predicted as 'safe' by well-established TCAD packages, radiation hardness can still be significantly degraded by a few lucky arsenic ions reaching the gate oxide during self-aligned CMOS source/drain ion implantation. The most likely explanation is that both oxide traps and interface traps are created when ions penetrate and damage the gate oxide after channeling or traveling along polysilicon grain boundaries during the implantation process.