Publications

Abstract not provided.

Assemblies produced by 3D Integration, whether fabricated at die or wafer level, involve a large number of post fab processing steps. Performing the prove-in of these operations on high value product has many limitations. This work uses simple surrogate process characterization vehicles, which workaround limitations of cost, timeliness of piecparts, ability to consider multiple processing options, and insufficient volumes for adequately exercising flows to collect specific process data for characterization. The test structures easily adapt to specific product in terms of die dimensions, aspect ratios, pitch and number of interconnects, and etc. This results in good fidelity in exercising product-specific processing. The discussed Cyclops vehicle implements a mirrored layout suitable for stacking to itself by wafer-to-wafer, die-to-wafer, or die-to-die. A standardized 2x10 pad test interface allows characterization of any of the integration methods with a single simple setup. This design offers the utility of comparison study of the various methods all using the same basis.

3D Integration approaches exist for wafer-to-wafer, die-towafer, and die-to-die assembly, each with distinct merits. Creation of "seamless" wafer scale focal plane arrays on the order of 6-8" in diameter drives very demanding yield requirements and understanding. This work established a Monte Carlo model of our exploratory architecture in order to assess the trades of the various assembly methods. The model results suggested an optimum die size, number of die stacks per assembly, number of layers per stack, and quantified the value of sorting for optimizing the assembly process.

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This paper presents the challenges and solutions of applying Built-In-Current Sensors (BICS) to a safety-critical IC design for the purpose of in-situ state-of-health monitoring. The developed Quiscent Current Monitor (QCM) system consists of multiple BISC and digital control logic. The QCM BICS can detect leakage current as low as 4 {micro}A, run at system speed, and has relatively low real estate overhead. The QCM digital logic incorporates extensive debug capability and Built-In-Self-Test (BIST). The authors performed analog and digital simulations of the integrated BICS, and performed layout and tapeout of the design. Silicon is now in fabrication. Results to date show that, for some systems, BICS can be a practical and relatively inexpensive method for providing state-of-health monitoring of safety-critical microelectronics.