The defect density present at the dielectric-semiconductor interface in an MOS structure directly influences the channel carrier characteristics in semiconductor devices, especially in wide bandgap material systems used in power devices. While these trap defects are typically quantified through electrical characterization of MOS-capacitor test structures, this treatment offers very little insight into the physical nature of interface defects. Such shortcomings demand a physical characterization strategy to guide fabrication optimization. X-ray photoelectron spectroscopy (XPS) is suggested as a viable technique to determine chemical data for dielectric interfaces formed using atomic layer deposition (ALD) on GaN substrates. Previously, 1-D XPS characterization has confirmed the presence of a GaxOy interlayer between ALD dielectrics and the GaN substrate. In this work, XPS data is serially collected to form 2-D images of an ALD-Al2O3/GaN interface as a proof-of-concept experiment for in-situ XPS quality monitoring during ALD processing. The information provided by this work reveals some of the challenges for incorporating XPS characterization as an in-situ strategy during fabrication of GaN-based devices. Separately, electrical mapping of a 2-D array of ALD-Al2O3/GaN MOS-capacitor devices provide a means to quantify the spatial variations in interface quality across a single wafer. Physical characterization techniques, such as time-of-flight secondary ion mass spectroscopy, provide additional chemical information about the Al2O3/GaxOy/GaN structure that complement the electrical mapping results. This analysis shows that a higher GaxOy content correlates with higher interface state defects for trap energies deep in the band gap.
Characterizing interface trap states in commercial wide bandgap devices using frequency-based measurements requires unconventionally high probing frequencies to account for both fast and slow traps associated with wide bandgap materials. The C − ψ S technique has been suggested as a viable quasi-static method for determining the interface trap state densities in wide bandgap systems, but the results are shown to be susceptible to errors in the analysis procedure. This work explores the primary sources of errors present in the C − ψ S technique using an analytical model that describes the apparent response for wide bandgap MOS capacitor devices. Measurement noise is shown to greatly impact the linear fitting routine of the 1 / C S ∗ 2 vs ψ S plot to calibrate the additive constant in the surface potential/gate voltage relationship, and an inexact knowledge of the oxide capacitance is also shown to impede interface trap state analysis near the band edge. In addition, a slight nonlinearity that is typically present throughout the 1 / C S ∗ 2 vs ψ S plot hinders the accurate estimation of interface trap densities, which is demonstrated for a fabricated n-SiC MOS capacitor device. Methods are suggested to improve quasi-static analysis, including a novel method to determine an approximate integration constant without relying on a linear fitting routine.
