The recipients of the 2014 NSREC Outstanding Conference Paper Award are Nathaniel A. Dodds, James R. Schwank, Marty R. Shaneyfelt, Paul E. Dodd, Barney L. Doyle, Michael Trinczek, Ewart W. Blackmore, Kenneth P. Rodbell, Michael S. Gordon, Robert A. Reed, Jonathan A. Pellish, Kenneth A. LaBel, Paul W. Marshall, Scot E. Swanson, Gyorgy Vizkelethy, Stuart Van Deusen, Frederick W. Sexton, and M. John Martinez, for their paper entitled "Hardness Assurance for Proton Direct Ionization-Induced SEEs Using a High-Energy Proton Beam." For older CMOS technologies, protons could only cause single-event effects (SEEs) through nuclear interactions. Numerous recent studies on 90 nm and newer CMOS technologies have shown that protons can also cause SEEs through direct ionization. Furthermore, this paper develops and demonstrates an accurate and practical method for predicting the error rate caused by proton direct ionization (PDI).
The low-energy proton energy spectra of all shielded space environments have the same shape. This shape is easily reproduced in the laboratory by degrading a high-energy proton beam, producing a high-fidelity test environment. We use this test environment to dramatically simplify rate prediction for proton direct ionization effects, allowing the work to be done at high-energy proton facilities, on encapsulated parts, without knowledge of the IC design, and with little or no computer simulations required. Proton direct ionization (PDI) is predicted to significantly contribute to the total error rate under the conditions investigated. Scaling effects are discussed using data from 65-nm, 45-nm, and 32-nm SOI SRAMs. These data also show that grazing-angle protons will dominate the PDI-induced error rate due to their higher effective LET, so PDI hardness assurance methods must account for angular effects to be conservative. As a result, we show that this angular dependence can be exploited to quickly assess whether an IC is susceptible to PDI.
This work presents experimental SEGR data for MOS-devices, where the gate dielectrics are are made of stacked SiO2–Si3N4 structures. Also a semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is proposed. Then statistical interrelationship between SEGR cross-section data and simulated energy deposition probabilities in thin dielectric layers is discussed.
Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS
Schwank, James R.; Shaneyfelt, Marty R.; Ferlet-Cavrois, Véronique; Dodd, Paul E.; Blackmore, Ewart W.; Pellish, Jonathan A.; Rodbell, Kenneth P.; Heidel, David F.; Marshall, Paul W.; LaBel, Kenneth A.; Gouker, Pascale M.; Tam, Nelson; Wong, Richard; Wen, Shi J.; Reed, Robert A.; Dalton, Scott M.; Swanson, Scot E.
A series of experiments on the MEDUSA linear accelerator radiation test facility were performed to evaluate the difference in dose measured using different methods. Significant differences in dosimeter-measured radiation dose were observed for the different dosimeter types for the same radiation environments, and the results are compared and discussed in this report.
The amounts of charge collection by single-photon absorption to that by two-photon absorption laser testing techniques have been directly compared using specially made SOI diodes. Details of this comparison are discussed.
Large and unexpected radiation-induced voltage shifts have been observed for some MOS technologies exposed to moisture. The mechanisms for these large voltage shifts and their implications for long-term aging are discussed.
The total dose hardness of several commercial power MOSFET technologies is examined. After exposure to 20 krad(SiO{sub 2}) most of the n- and p-channel devices examined in this work show substantial (2 to 6 orders of magnitude) increases in off-state leakage current. For the n-channel devices, the increase in radiation-induced leakage current follows standard behavior for moderately thick gate oxides, i.e., the increase in leakage current is dominated by large negative threshold voltage shifts, which cause the transistor to be partially on even when no bias is applied to the gate electrode. N-channel devices biased during irradiation show a significantly larger leakage current increase than grounded devices. The increase in leakage current for the p-channel devices, however, was unexpected. For the p-channel devices, it is shown using electrical characterization and simulation that the radiation-induced leakage current increase is related to an increase in the reverse bias leakage characteristics of the gated diode which is formed by the drain epitaxial layer and the body. This mechanism does not significantly contribute to radiation-induced leakage current in typical p-channel MOS transistors. The p-channel leakage current increase is nearly identical for both biased and grounded irradiations and therefore has serious implications for long duration missions since even devices which are usually powered off could show significant degradation and potentially fail.
This paper investigates the transient response of 50-nm gate length fully and partially depleted SOI and bulk devices to pulsed laser and heavy ion microbeam irradiations. The measured transient signals on 50-nm fully depleted devices are very short, and the collected charge is small compared to older 0.25-{micro}m generation SOI and bulk devices. We analyze in detail the influence of the SOI architecture (fully or partially depleted) on the pulse duration and the amount of bipolar amplification. For bulk devices, the doping engineering is shown to have large effects on the duration of the transient signals and on the charge collection efficiency.
Microelectronic devices in satellites and spacecraft are exposed to high energy cosmic radiation. Furthermore, Earth-based electronics can be affected by terrestrial radiation. The radiation causes a variety of Single Event Effects (SEE) that can lead to failure of the devices. High energy heavy ion beams are being used to simulate both the cosmic and terrestrial radiation to study radiation effects and to ensure the reliability of electronic devices. Broad beam experiments can provide a measure of the radiation hardness of a device (SEE cross section) but they are unable to pinpoint the failing components in the circuit. A nuclear microbeam is an ideal tool to map SEE on a microscopic scale and find the circuit elements (transistors, capacitors, etc.) that are responsible for the failure of the device. In this paper a review of the latest radiation effects microscopy (REM) work at Sandia will be given. Different SEE mechanisms (Single Event Upset, Single Event Transient, etc.) and the methods to study them (Ion Beam Induced Charge (IBIC), Single Event Upset mapping, etc.) will be discussed. Several examples of using REM to study the basic effects of radiation in electronic devices and failure analysis of integrated circuits will be given.
This paper analyzes the collected charge in heavy ion irradiated MOS structures. The charge generated in the substrate induces a displacement effect which strongly depends on the capacitor structure. Networks of capacitors are particularly sensitive to charge sharing effects. This has important implications for the reliability of SOI and DRAMs which use isolation oxides as a key elementary structure. The buried oxide of present day and future SOI technologies is thick enough to avoid a significant collection from displacement effects. On the other hand, the retention capacitors of trench DRAMs are particularly sensitive to charge release in the substrate. Charge collection on retention capacitors participate to the MBU sensitivity of DRAM.
Mechanisms for enhanced low-dose-rate sensitivity are described. In these mechanisms, bimolecular reactions dominate the kinetics at high dose rates thereby causing a sub-linear dependence on total dose, and this leads to a dose-rate dependence. These bimolecular mechanisms include electron-hole recombination, hydrogen recapture at hydrogen source sites, and hydrogen dimerization to form hydrogen molecules. The essence of each of these mechanisms is the dominance of the bimolecular reactions over the radiolysis reaction at high dose rates. However, at low dose rates, the radiolysis reaction dominates leading to a maximum effect of the radiation.
We examine the total-dose radiation response of capacitors and transistors with stacked Al{sub 2}O{sub 3} on oxynitride gate dielectrics with Al and poly-Si gates after irradiation with 10 keV X-rays. The midgap voltage shift increases monotonically with dose and depends strongly on both Al{sub 2}O{sub 3} and SiO{sub x}N{sub y} thickness. The thinnest dielectrics, of most interest to industry, are extremely hard to ionizing irradiation, exhibiting only {approx}50 mV of shift at a total dose of 10 Mrad(SiO{sub 2}) for the worst case bias condition. Oxygen anneals are found to improve the total dose radiation response by {approx}50% and induce a small amount of capacitance-voltage hysteresis. Al{sub 2}O{sub 3}/SiO{sub x}N{sub y} dielectrics which receive a {approx}1000 C dopant activation anneal trap {approx}12% more of the initial charge than films annealed at 550 C. Charge pumping measurements show that the interface trap density decreases with dose up to 500 krad(SiO{sub 2}). This surprising result is discussed with respect to hydrogen effects in alternative dielectric materials, and may be the result of radiation-induced hydrogen passivation of some of the near-interfacial defects in these gate dielectrics.
It is shown that final chip passivation layers can have a significant impact on total dose hardness. A number of final chip passivation layers are evaluated to identify films that mitigate enhanced low-dose-rate sensitivity (ELDRS) in National Semiconductor Corporation's linear bipolar technologies. It is shown that devices fabricated with either a low temperature oxide or a tetraethyl ortho silicate passivation do not exhibit significant ELDRS effects up to 100 krad(SiO{sub 2}). Passivation studies on CMOS SRAMs suggest that it is unlikely that the passivation layers (or processing tools) are acting as a new source of hydrogen, which could drift or diffuse into the oxide and increase ELDRS sensitivity. Instead, it is possible that the passivation layers affect the mechanical stress in the oxide, which may affect oxide trap properties and possibly the release and mobility of hydrogen. Correlations between mechanical stress induced by the passivation layers and radiation degradation are discussed.
High-energy ion-irradiated 3.3-nm oxynitride film and 2.2-nm SiO2-film MOS capacitors show premature break-down during subsequent electrical stress. This degradation in breakdown increases with increasing ion linear energy transfer (LET), increasing ion fluence, and decreasing oxide thickness. The reliability degradation due to high-energy ion-induced latent defects is explained by a simple percolation model of conduction through SiO2 layers with irradiation and/or electrical stress-induced defects. Monitoring the gate-leakage current reveals the presence of latent defects in the dielectric films. These results may be significant to future single-event effects and single-event gate rupture tests for MOS devices and ICs with ultrathin gate oxides.
The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-Dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMS, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMS is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.
Metal-oxide-silicon capacitors fabricated in a bi-polar process were examined for densities of oxide trapped charge, interface traps and deactivated substrate acceptors following high-dose-rate irradiation at 100 C. Acceptor neutralization near the Si surface occurs most efficiently for small irradiation biases in depletion. The bias dependence is consistent with compensation and passivation mechanisms involving the drift of H{sup +} ions in the oxide and Si layers and the availability of holes in the Si depletion region. Capacitor data from unbiased irradiations were used to simulate the impact of acceptor neutralization on the current gain of an npn bipolar transistor. Neutralized acceptors near the base surface enhance current gain degradation associated with radiation-induced oxide trapped charge and interface traps by increasing base recombination. The additional recombination results from the convergence of carrier concentrations in the base and increased sensitivity of the base to oxide trapped charge. The enhanced gain degradation is moderated by increased electron injection from the emitter. These results suggest that acceptor neutralization may enhance radiation-induced degradation of linear circuits at elevated temperatures.
The worst case bias during total dose irradiation of partially depleted SOI transistors (from SNL and from CEA/LETI) is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.
Dopant deactivation at 100 C is measured in bipolar Si-SiO{sub 2} structures as a function of irradiation bias. The deactivation occurs most efficiently at small biases in depletion and is consistent with passivation and compensation mechanisms involving hydrogen.
SEU is studied in SOI transistors and circuits with various body tie structures. The importance of impact ionization effects, including single-event snapback, is explored. Implications for hardness assurance testing of SOI integrated circuits are discussed.
Large differences in charge buildup in SOI buried oxides can result between x-ray and Co-60 irradiations. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored.
Thermal-stress effects are shown to have a significant impact on the enhanced low-dose-rate sensitivity of linear bipolar circuits. Implications of these results on hardness assurance testing and mechanisms are discussed.
Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.
Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it is likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance.
Recent space experience has shown that the use of commercial optocouplers can be problematic in spacecraft, such as TOPEX/Poseidon, that must operate in significant radiation environments. Radiation--induced failures of these devices have been observed in space and have been further documented at similar radiation doses in the laboratory. The ubiquitous use of optocouplers in spacecraft systems for a variety of applications, such as electrical isolation, switching and power transfer, is indicative of the need for optocouplers that can withstand the space radiation environment. In addition, the distributed nature of their use implies that it is not particularly desirable to shield optocouplers for use in radiation environments. Thus, it will be important for the space community to have access to radiation hardened/tolerant optocouplers. For many microelectronic and photonic devices, it is difficult to achieve radiation hardness without sacrificing performance. However, in the case of optocouplers, one should be able to achieve both superior radiation hardness and performance for such characteristics as switching speed, current transfer ratio (CTR), minimum power usage and array power transfer, if standard light emitting diodes (LEDs), such as those in the commercial optocouplers mentioned above, are avoided, and VCSELs are employed as the emitter portion of the optocoupler. The physical configuration of VCSELs allows one to achieve parallel use of an array of devices and construct a multichannel optocoupler in the standard fashion with the emitters and detectors looking at each other. In addition, detectors similar in structure to the VCSELs can be fabricated which allows bidirectional functionality of the optocoupler. Recent discussions suggest that VCSELs will enjoy widespread applications in the telecommunications and data transfer fields.
A partially-depleted SOI transistor structure has been designed that does not require the use of specially-processed hardened buried oxides for total-dose hardness and maintains the intrinsic SEU and dose rate hardness advantages of SOI technology.
Trapping of mobile protons is observed in various SOI materials, but only upon irradiating under a positive top Si bias. Thermal detrapping shows that the proton traps are shallow and located near the substrate Si/SiO{sub 2} interface.
Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed.
Four general topics are covered in respect to the natural space radiation environment: (1) particles trapped by the earth`s magnetic field, (2) cosmic rays, (3) radiation environment inside a spacecraft, (4) laboratory radiation sources. The interaction of radiation with materials is described by ionization effects and displacement effects. Total-dose effects on MOS devices is discussed with respect to: measurement techniques, electron-hole yield, hole transport, oxide traps, interface traps, border traps, device properties, case studies and special concerns for commercial devices. Other device types considered for total-dose effects are SOI devices and nitrided oxide devices. Lastly, single event phenomena are discussed with respect to charge collection mechanisms and hard errors. (GHH)
Several different techniques are used to electrically characterize defects at or near the Si/SiO{sub 2} interface. Three common methods are the charge-pumping, midgap, and dual-transistor techniques. Each of these techniques offer advantages and disadvantages compared to the others. For instance, charge-pumping measurements are not significantly affected by charge lateral non-uniformities and can provide high-sensitivity measurements of the average density of interface traps. However, charge-pumping measurements cannot provide accurate measurements of the number of charged oxide traps. In contrast both the dual-tranistor and midgap techniques can provide good estimates for threshold-voltage shifts due to oxide traps and interface traps, but these estimates can break down when significant charge lateral non-uniformities are present in the oxide. Considering the widespread use of these, techniques, it is of practical and theoretical importance to quantitatively compare them. At the SISC, we will present a detailed comparison of the charge-pumping, midgap, and dual-tranistor techniques. Values for the density of interface traps measured using the three techniques will be compared for n- and P-channel transistors fabricated using several different process technologies, and under different process technologies, and under different irradiation and anneal conditions. Discrepancies between the different techniques are observed. Causes for the discrepancies will be explored at the SISC.
A large buildup in interface traps has been observed in commercial and radiation-hardened MOS transistors at very long times after irradiation (> 10{sup 6} s). This latent buildup may have important implications for CMOS response in space. 13 refs.
The effects of total-dose irradiation on PbO-ZrO{sub 2}-TiO{sub 2} ferroelectric capacitors have been studied in detail. It is shown that significant total-dose degradation of ferroelectrics can occur at dose levels greater than 1 Mrad(Si). 6 refs., 5 figs.
Radiation-induced interface traps in Si-gate MOS devices follow an E{sup {minus}1/2} electric field dependence for E {ge} +0.13 MV/cm when electron-hole recombination effects are included. A hybrid model involving hole trapping and hydrogen transport is suggested. 20 refs., 4 figs.
