Publications

Abstract not provided.

Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

Sub-optimal design practices can reduce the radiation hardness of a circuit even though it is fabricated in a radiation hardened process. This is especially true for a nonvolatile memory, as compared to a standard digital circuit, where high voltages and unusual bias conditions are required. This paper will discuss the design techniques used in the development of a 64K EEPROM (Electrically Erasable Programmable Read Only Memory) to maximize radiation hardness. The circuit radiation test results will be reviewed in order to provide validation of the techniques. © 1993 IEEE

Circumvention applications require a memory that retains data through radiation (total dose and transient) and loss of power. Various memory technologies have been reviewed and none, as yet, can meet these requirements. However, if complementary metal oxide silicon (CMOS) and silicon nitride oxide silicon (SNOS) memories are combined in a shadow RAM (random access memory) configuration, the requirements can be fulfilled. © 1991 IEEE

There has long been a need for fast read nonvolatile, rad hard memories for military and space applications. Recent advances in EEPROM technology now allow this need to be met for many applications. Harris/Sandia have developed a 16k and a 256k rad hard EEPROM. The EEPROMs utilize a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory transistor integrated into a 2 {mu}m, rad hard two level metal CMOS process. Both the 16k and the 256k parts have been designed to interface with the Intel 8085 or 80C51 and National 32000 series microprocessors and feature page and block clear modes. Both parts are functionally identical, and are produced by the same fabrication process. They are also pin for pin compatible with each other, except for the extra address and ground pins on the 256k. This paper describes the characteristics of this EEPROM family. 1 ref.