Publications

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Structural modularity is critical to solid-state transformer (SST) and solid-state power substation (SSPS) concepts, but operational aspects related to this modularity are not yet fully understood. Previous studies and demonstrations of modular power conversion systems assume identical module compositions, but dependence on module uniformity undercuts the value of the modular framework. In this project, a hierarchical control approach was developed for modular SSTs which achieves system-level objectives while ensuring equitable power sharing between nonuniform building block modules. This enables module replacements and upgrades which leverage circuit and device technology advancements to improve system-level performance. The functionality of the control approach is demonstrated in detailed time-domain simulations. Results of this project provide context and strategic direction for future LDRD projects focusing on technologies supporting the SST crosscut outcome of the resilient energy systems mission campaign.

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With evolving landscape of DC power transmission and distribution, a reliable and fast protection against faults is critical, especially for medium- and high-voltage applications. Thus, solid-state circuit breakers (SSCB), consisting of cascaded silicon carbide (SiC) junction field-effect transistors (JFET), utilize the intrinsic normally-ON characteristic along with their low ON-resistance. This approach provides an efficient and robust protection solution from detrimental short-circuit events. However, for applications that require high-voltage blocking capability, a proper number of JFETs need be connected in series to achieve the desired blocking voltage rating. Ensuring equal voltage balancing across the JFETs during the switching transitions as well as the blocking stage is critical and hence, this paper presents a novel passive balancing network for series connected JFETs for DC SSCB applications. The dynamic voltage balancing network to synchronize both the turn ON and OFF intervals is described analytically. Moreover, the static voltage balancing network is implemented to establish equal sharing of the total blocking voltage across the series connection of JFETs. The proposed dynamic and steady-state balancing networks are validated by SPICE simulation and experimental results.

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In spite of several advantages of SiC JFETs over enhancement mode SiC MOSFETs, the intrinsic normally-ON characteristic of the JFETs can be undesirable for many industrial power conversion applications due to the negative turn-OFF voltage requirement. This prevents normally-ON JFETs from being widely accepted in industry. However, a cascode configuration, which uses a low voltage (LV) Si MOSFET can be used to enable a normally-OFF behavior, making this approach an attractive solution to utilize the benefits of SiC JFETs. For medium-, and high-voltage applications that require larger blocking voltage than the rating of each JFET, additional devices can be connected in series to increase the overall blocking voltage capability, creating a super-cascode configuration. This paper provides a review of several super-cascode topology variations and presents a comprehensive comparative study, evaluating similarities and differences in operating principles, equivalent circuits, and design considerations and limitations.

Optimized designs were achieved using a genetic algorithm to evaluate multi-objective trade space, including Mean-Time-Between-Failure (MTBF) and volumetric power density. This work provides a foundational platform that can be used to optimize additional power converters, such as an inverter for the EV traction drive system as well as trade-offs in thermal management due to the use of different device substrate materials.

In power electronic applications, reliability and power density are a few of the many important performance metrics that require continual improvement in order to meet the demand of today's complex electrical systems. However, due to the complexity of the synergy between various components, it is challenging to visualize and evaluate the effects of choosing one component over another and what certain design parameters impose on the overall reliability and lifetime of the system. Furthermore, many areas of electronics have realized remarkable innovation in the integration of new materials of passive and active components; wide-bandgap semiconductor devices and new magnetic materials allow higher operating temperature, blocking voltage, and switching frequency; all of which enable much more compact power converter designs. However, uncertainty remains in the overall electronics reliability in different design variations. Hence, in order to better understand the relationship between reliability and power density in a power electronic system, this paper utilizes a genetic algorithm (GA) to provide pareto optimal solution sets in a multi-variate trade space that relates the Mean Time Between Failures (MTBF) and volumetric power density for the design of a 5 kW synchronous boost converter. Different designs of the synchronous boost converter based on the variation of the electrical parameters and material types for the passive (input and output capacitors, the boost inductor, and the heatsink) and active components (switches) have been studied. A few candidate designs have been evaluated and verified through hardware experiments.

This paper describes the design of a very high power density inverter drive module using aggressive high-frequency design methods and multi-objective optimization tools. This work is part of a larger effort to develop electric drive designs with >97% efficiency, power densities of 100 kW/L for the power electronics, and with predicted reliable operation to 300, 000 miles. The approach taken in this work is to develop designs that utilize wide band gap devices (SiC or GaN) and ceramic capacitors to enable high-frequency switching and a compact integrated design. The multi-objective optimization is employed to select key parameters for the design.

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