The deeply depleted graphene-oxide-semiconductor (D2GOS) junction detector provides an effective architecture for photodetection, enabling direct readout of photogenerated charge. Because of an inherent gain mechanism proportional to graphene's high mobility (μ), this detector architecture exhibits large responsivities and signal-to-noise ratios (SNR). The ultimate sensitivity of the D2GOS junction detector may be limited, however, because of the generation of dark charge originating from interface states at the semiconductor/dielectric junction. Here, we examine the performance limitations caused by dark charge and demonstrate its mitigation via the creation of low interface defect junctions enabled by surface passivation. The resulting devices exhibit responsivities exceeding 10 000 A/W - a value which is 10× greater than that of analogous devices without the passivating thermal oxide. With cooling of the detector, the responsivity further increases to over 25 000 A/W, underscoring the impact of surface generation on performance and thus the necessity of minimizing interfacial defects for this class of photodetector.
Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibit a larger change in off-state leakage current. The "worst-case" bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.
Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibit a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.
This report summaries the work of a 2-year LDRD project aimed at using graphene in integrated circuits in ways that would both obfuscate their function and enhance their level of trust. We have studied (both experimentally and theoretically) process steps, optical properties, design/layout of circuits, and many kinds of analytical techniques. Our conclusion is that graphene shows promise in this application, but additional work must be done to improve compatibility with existing CMOS manufacturing facilities particularly in the area of contamination.