Publications

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Under conditions that were predicted as 'safe' by well-established TCAD packages, radiation hardness can still be significantly degraded by a few lucky arsenic ions reaching the gate oxide during self-aligned CMOS source/drain ion implantation. The most likely explanation is that both oxide traps and interface traps are created when ions penetrate and damage the gate oxide after channeling or traveling along polysilicon grain boundaries during the implantation process.

The total dose hardness of several commercial power MOSFET technologies is examined. After exposure to 20 krad(SiO{sub 2}) most of the n- and p-channel devices examined in this work show substantial (2 to 6 orders of magnitude) increases in off-state leakage current. For the n-channel devices, the increase in radiation-induced leakage current follows standard behavior for moderately thick gate oxides, i.e., the increase in leakage current is dominated by large negative threshold voltage shifts, which cause the transistor to be partially on even when no bias is applied to the gate electrode. N-channel devices biased during irradiation show a significantly larger leakage current increase than grounded devices. The increase in leakage current for the p-channel devices, however, was unexpected. For the p-channel devices, it is shown using electrical characterization and simulation that the radiation-induced leakage current increase is related to an increase in the reverse bias leakage characteristics of the gated diode which is formed by the drain epitaxial layer and the body. This mechanism does not significantly contribute to radiation-induced leakage current in typical p-channel MOS transistors. The p-channel leakage current increase is nearly identical for both biased and grounded irradiations and therefore has serious implications for long duration missions since even devices which are usually powered off could show significant degradation and potentially fail.

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This paper demonstrates a simple technique for building n-channel MOSFETs and complex micromechanical systems simultaneously instead of serially, allowing a more straightforward integration of complete systems. The fabrication sequence uses few additional process steps and only one additional masking layer compared to a MEMS-only technology. The process flow forms the MOSFET gate electrode using the first level of mechanical polycrystalline silicon, while the MOSFET source and drain regions are formed by dopant diffusions into the substrate from subsequent levels of heavily doped poly that is used for mechanical elements. The process yields devices with good, repeatable electrical characteristics suitable for a wide range of digital and analog applications.

Fast and quantitative analysis of cellular activity, signaling and responses to external stimuli is a crucial capability and it has been the goal of several projects focusing on patch clamp measurements. To provide the maximum functionality and measurement options, we have developed a patch clamp array device that incorporates on-chip electronics, mechanical, optical and microfluidic coupling as well as cell localization through fluid flow. The preliminary design, which integrated microfluidics, electrodes and optical access, was fabricated and tested. In addition, new designs which further combine mechanical actuation, on-chip electronics and various electrode materials with the previous designs are currently being fabricated.

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The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-Dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMS, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMS is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

SEU is studied in SOI transistors and circuits with various body tie structures. The importance of impact ionization effects, including single-event snapback, is explored. Implications for hardness assurance testing of SOI integrated circuits are discussed.

Large differences in charge buildup in SOI buried oxides can result between x-ray and Co-60 irradiations. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored.

Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

We report in this paper a study of the effective mass in thin oxide Si-MOSFETs, using the temperature dependence of the Shubnikov-de Haas (SdH) effect and following the methodology developed by Smith and Stiles.

We discuss the use of light scattered from a latent image to control photoresist exposure dose and focus conditions which results in improved control of the critical dimension (CD) of the developed photoresist. A laser at a non-exposing wavelength is used to illuminate a latent image grating. The light diffracted from the grating is directly related to the exposure dose and focus and thus to the resultant CD in the developed resist. Modeling has been done using rigorous coupled wave analysis to predict the diffraction from a latent image as a function of the substrate optical properties and the photoactive compound (PAC) concentration distribution inside the photoresist. It is possible to use the model to solve the inverse problem: given the diffraction, to predict the parameters of the latent image and hence the developed pattern. This latent image monitor can be implemented in a stepper to monitor exposure in situ, or prior to development to predict the developed CD of a wafer for early detection of bad devices. Experimentation has been conducted using various photoresists and substrates with excellent agreement between theoretical and experimental results. The technique has been used to characterize a test pattern with a focused spot as small as 36{mu}m in diameter. Using diffracted light from a simulated closed-loop control of exposure dose, CD control was improved by as much as 4 times for substrates with variations in underlying film thickness, compared to using fixed exposure time. The latent image monitor has also been applied to wafers with rough metal substrates and focus optimization.