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Investigation of interfacial impurities in m-plane GaN regrown p-n junctions for high-power vertical electronic devices

Proceedings of SPIE - The International Society for Optical Engineering

Stricklin, Isaac; Monavarian, Morteza; Aragon, Andrew; Pickrell, Gregory P.; Crawford, Mary H.; Allerman, A.A.; Armstrong, Andrew A.; Feezell, Daniel

GaN is an attractive material for high-power electronics due to its wide bandgap and large breakdown field. Verticalgeometry devices are of interest due to their high blocking voltage and small form factor. One challenge for realizing complex vertical devices is the regrowth of low-leakage-current p-n junctions within selectively defined regions of the wafer. Presently, regrown p-n junctions exhibit higher leakage current than continuously grown p-n junctions, possibly due to impurity incorporation at the regrowth interfaces, which consist of c-plane and non-basal planes. Here, we study the interfacial impurity incorporation induced by various growth interruptions and regrowth conditions on m-plane p-n junctions on free-standing GaN substrates. The following interruption types were investigated: (1) sample in the main MOCVD chamber for 10 min, (2) sample in the MOCVD load lock for 10 min, (3) sample outside the MOCVD for 10 min, and (4) sample outside the MOCVD for one week. Regrowth after the interruptions was performed on two different samples under n-GaN and p-GaN growth conditions, respectively. Secondary ion mass spectrometry (SIMS) analysis indicated interfacial silicon spikes with concentrations ranging from 5e16 cm-3 to 2e18 cm-3 for the n-GaN growth conditions and 2e16 cm-3 to 5e18 cm-3 for the p-GaN growth conditions. Oxygen spikes with concentrations ∼1e17 cm-3 were observed at the regrowth interfaces. Carbon impurity levels did not spike at the regrowth interfaces under either set of growth conditions. We have correlated the effects of these interfacial impurities with the reverse leakage current and breakdown voltage of regrown m-plane p-n junctions.

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TYPE Conference Poster YEAR 2018
DOIOSTIScopus

Planar Ohmic Contacts to Al 0.45 Ga 0.55 N/Al 0.3 Ga 0.7 N High Electron Mobility Transistors

ECS Journal of Solid State Science and Technology

Klein, Brianna A.; Baca, A.G.; Armstrong, Andrew A.; Allerman, A.A.; Sanchez, Carlos A.; Douglas, Erica A.; Crawford, Mary H.; Miller, Mary A.; Kotula, Paul G.; Fortune, Torben R.; Abate, Vincent M.

Here, we present a low resistance, straightforward planar ohmic contact for Al0.45Ga0.55N/Al0.3Ga0.7N high electron mobility transistors. Five metal stacks (a/Al/b/Au; a = Ti, Zr, V, Nb/Ti; b = Ni, Mo, V) were evaluated at three individual annealing temperatures (850, 900, and 950°C). The Ti/Al/Ni/Au achieved the lowest specific contact resistance at a 900°C anneal temperature. Transmission electron microscopy analysis revealed a metal-semiconductor interface of Ti-Al-Au for an ohmic (900°C anneal) and a Schottky (850°C anneal) Ti/Al/Ni/Au stack. HEMTs were fabricated using the optimized recipe with resulting contacts that had room-temperature specific contact resistances of ρc = 2.5 × 10-5 Ω cm², sheet resistances of RSH = 3.9 kΩ/$\blacksquare$, and maximum current densities of 75 mA/mm (at VGATE of 2 V). Electrical measurements from -50 to 200°C had decreasing specific contact resistance and increasing sheet resistance, with increasing temperature. These contacts enabled state-of-the-art performance of Al0.45Ga0.55N/Al0.3Ga0.7N HEMTs.

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TYPE Journal Article YEAR 2017
DOIOSTIDOIOSTI
Results 76–100 of 258
Results 76–100 of 258