The design, simulation, fabrication, packaging, electrical characterization and testing analysis of a microfabricated a cylindrical ion trap ({mu}CIT) array is presented. Several versions of microfabricated cylindrical ion traps were designed and fabricated. The final design of the individual trap array element consisted of two end cap electrodes, one ring electrode, and a detector plate, fabricated in seven tungsten metal layers by molding tungsten around silicon dioxide (SiO{sub 2}) features. Each layer of tungsten is then polished back in damascene fashion. The SiO{sub 2} was removed using a standard release processes to realize a free-hung structure. Five different sized traps were fabricated with inner radii of 1, 1.5, 2, 5 and 10 {micro}m and heights ranging from 3-24 {micro}m. Simulations examined the effects of ion and neutral temperature, the pressure and nature of cooling gas, ion mass, trap voltage and frequency, space-charge, fabrication defects, and other parameters on the ability of micrometer-sized traps to store ions. The electrical characteristics of the ion trap arrays were determined. The capacitance was 2-500 pF for the various sized traps and arrays. The resistance was in the order of 1-2 {Omega}. The inductance of the arrays was calculated to be 10-1500 pH, depending on the trap and array sizes. The ion traps' field emission characteristics were assessed. It was determined that the traps could be operated up to 125 V while maintaining field emission currents below 1 x 10{sup -15} A. The testing focused on using the 5-{micro}m CITs to trap toluene (C{sub 7}H{sub 8}). Ion ejection from the traps was induced by termination of the RF voltage applied to the ring electrode and current measured on the collector electrode suggested trapping of ions in 1-10% of the traps. Improvements to the to the design of the traps were defined to minimize voltage drop to the substrate, thereby increasing trapping voltage applied to the ring electrode, and to allow for electron injection into, ion ejection from, and optical access to the trapping region.
A three-dimensional tungsten photonic crystal is thermally excited and shown to emit light at a narrow band, {lambda} = 3.3-4.25 {micro}m. The emission is experimentally observed to exceed that of the free-space Planck radiation over a wide temperature range, T = 475-850 K. it is proposed that an enhanced density of state associated with the propagating electromagnetic Bloch waves in the photonic crystal is responsible for this experimental finding.
Radio frequency microelectromechanical systems (RF MEMS) are an enabling technology for next-generation communications and radar systems in both military and commercial sectors. RF MEMS-based reconfigurable circuits outperform solid-state circuits in terms of insertion loss, linearity, and static power consumption and are advantageous in applications where high signal power and nanosecond switching speeds are not required. We have demonstrated a number of RF MEMS switches on high-resistivity silicon (high-R Si) that were fabricated by leveraging the volume manufacturing processes available in the Microelectronics Development Laboratory (MDL), a Class-1, radiation-hardened CMOS manufacturing facility. We describe novel tungsten and aluminum-based processes, and present results of switches developed in each of these processes. Series and shunt ohmic switches and shunt capacitive switches were successfully demonstrated. The implications of fabricating on high-R Si and suggested future directions for developing low-loss RF MEMS-based circuits are also discussed.
In this work we have demonstrated the fabrication of two different classes of devices which demonstrate the integration of simple MEMS structures with photonics structures. In the first class of device a suspended, movable Si waveguide was designed and fabricated. This waveguide was designed to be able to be actuated so that it could be brought into close proximity to a ring resonator or similar structure. In the course of this work we also designed a technique to improve the input coupling to the waveguide. While these structures were successfully fabricated, post fabrication and testing involved a significant amount of manipulation of the devices and due to their relatively flimsy nature our structures could not readily survive this extra handling. As a result we redesigned our devices so that instead of moving the waveguides themselves we moved a much smaller optical element into close proximity to the waveguides. Using this approach it was also possible to fabricate a much larger array of actively switched photonic devices: switches, ring resonators, couplers (which act as switches or splitters) and attenuators. We successfully fabricated all these structures and were able to successfully demonstrate splitters, switches and attenuators. The quality of the SiN waveguides fabricated in this work were found to be qualitatively compatible to those made using semiconductor materials.
We present our research results on membrane pores. The study was divided into two primary sections. The first involved the formation of protein pores in free-standing lipid bilayer membranes. The second involved the fabrication via surface micromachining techniques and subsequent testing of solid-state nanopores using the same characterization apparatus and procedures as that used for the protein pores. We were successful in our ability to form leak-free lipid bilayers, to detect the formation of single protein pores, and to monitor the translocation dynamics of individual homogeneous 100 base strands of DNA. Differences in translocation dynamics were observed when the base was switched from adenine to cytosine. The solid state pores (2-5 nm estimated) were fabricated in thin silicon nitride membranes. Testing of the solid sate pores indicated comparable currents for the same size protein pore with excellent noise and sensitivity. However, there were no conditions under which DNA translocation was observed. After considerable effort, we reached the unproven conclusion that multiple (<1 nm) pores were formed in the nitride membrane, thus explaining both the current sensitivity and the lack of DNA translocation blockages.
A three-dimensional tungsten photonic crystal is experimentally realized with a complete photonic band gap at wavelengths {lambda} {ge} 3 {micro}m. At an effective temperature of <T> {approx} 1535 K, the photonic crystal exhibits a sharp emission at {approx}1.5 {micro}m and is promising for thermal photovoltaic (TPV) power generation. Based on the spectral radiance, a proper length scaling and a planar TPV model calculation, an optical-to-electric conversion efficiency of {approx}34% and electrical power of {approx}14 W/cm{sup 2} is theoretically possible.
Thermophotovoltaics (TPV) converts the radiant energy of a thermal source into electrical energy using photovoltaic cells. TPV has a number of attractive features, including: fuel versatility (nuclear, fossil, solar, etc.), quiet operation, low maintenance, low emissions, light weight, high power density, modularity, and possibility for cogeneration of heat and electricity. Some of these features are highly attractive for military applications (Navy and Army). TPV could also be used for distributed power and automotive applications wherever fuel cells, microturbines, or cogeneration are presently being considered if the efficiencies could be raised to around 30%. This proposal primarily examine approaches to improving the radiative efficiency. The ideal irradiance for the PV cell is monochromatic illumination at the bandgap. The photonic crystal approach allows for the tailoring of thermal emission spectral bandwidth at specific wavelengths of interest. The experimental realization of metallic photonic crystal structures, the optical transmission, reflection and absorption characterization of it have all been carried out in detail and will be presented next. Additionally, comprehensive models of TPV conversion has been developed and applied to the metallic photonic crystal system.
This report outlines our work on the integration of high efficiency photonic lattice structures with MEMS (MicroElectroMechanical Systems). The simplest of these structures were based on 1-D mirror structures. These were integrated into a variety of devices, movable mirrors, switchable cavities and finally into Bragg fiber structures which enable the control of light in at least 2 dimensions. Of these devices, the most complex were the Bragg fibers. Bragg fibers consist of hollow tubes in which light is guided in a low index media (air) and confined by surrounding Bragg mirror stacks. In this work, structures with internal diameters from 5 to 30 microns have been fabricated and much larger structures should also be possible. We have demonstrated the fabrication of these structures with short wavelength band edges ranging from 400 to 1600nm. There may be potential applications for such structures in the fields of integrated optics and BioMEMS. We have also looked at the possibility of waveguiding in 3 dimensions by integrating defects into 3-dimensional photonic lattice structures. Eventually it may be possible to tune such structures by mechanically modulating the defects.
Photonic crystals are periodically engineered ''materials'' which are the photonic analogues of electronic crystals. Much like electronic crystal, photonic crystal materials can have a variety of crystal symmetries, such as simple-cubic, closed-packed, Wurtzite and diamond-like crystals. These structures were first proposed in late 1980's. However, due mainly to fabrication difficulties, working photonic crystals in the near-infrared and visible wavelengths are only just emerging. In this article, we review the construction of two- and three-dimensional photonic crystals of different symmetries at infrared and optical wavelengths using advanced semiconductor processing. We further demonstrate that this process lends itself to the creation of line defects (linear waveguides) and point defects (micro-cavities), which are the most basic building blocks for optical signal processing, filtering and routing.
This LDRD is aimed to place Sandia at the forefront of GaN-based technologies. Two important themes of this LDRD are: (1) The demonstration of novel GaN-based devices which have not yet been much explored and yet are coherent with Sandia's and DOE's mission objectives. UV optoelectronic and piezoelectric devices are just two examples. (2) To demonstrate front-end monolithic integration of GaN with Si-based microelectronics. Key issues pertinent to the successful completion of this LDRD have been identified to be (1) The growth and defect control of AlGaN and GaN, and (2) strain relief during/after the heteroepitaxy of GaN on Si and the separation/transfer of GaN layers to different wafer templates.
Failure analysis (FA) tools have been applied to analyze tungsten coated polysilicon microengines. These devices were stressed under accelerated conditions at ambient temperatures and pressure. Preliminary results illustrating the failure modes of microengines operated under variable humidity and ultra-high drive frequency will also be shown. Analysis of tungsten coated microengines revealed the absence of wear debris in microengines operated under ambient conditions. Plan view imaging of these microengines using scanning electron microscopy (SEM) revealed no accumulation of wear debris on the surface of the gears or ground plane on microengines operated under standard laboratory conditions. Friction bearing surfaces were exposed and analyzed using the focused ion beam (FIB). These cross sections revealed no accumulation of debris along friction bearing surfaces. By using transmission electron microscopy (TEM) in conjunction with electron energy loss spectroscopy (EELS), we were able to identify the thickness, elemental analysis, and crystallographic properties of tungsten coated MEMS devices. Atomic force microscopy was also utilized to analyze the surface roughness of friction bearing surfaces.
Two major problems associated with Si-based MEMS (MicroElectroMechanical Systems) devices are stiction and wear. Surface modifications are needed to reduce both adhesion and friction in micromechanical structures to solve these problems. In this paper, we will present a CVD (Chemical Vapor Deposition) process that selectively coats MEMS devices with tungsten and significantly enhances device durability. Tungsten CVD is used in the integrated-circuit industry, which makes this approach manufacturable. This selective deposition process results in a very conformal coating and can potentially address both stiction and wear problems confronting MEMS processing. The selective deposition of tungsten is accomplished through the silicon reduction of WF6. The self-limiting nature of this selective. We deposition process ensures the consistency necessary for process control. The tungsten is deposited after the removal of the sacrificial oxides to minimize stress and process integration problems. Tungsten coating adheres well and is hard and conducting, requirements for device performance. Furthermore, since the deposited tungsten infiltrates under adhered silicon parts and the volume of W deposited is less than the amount of Si consumed, it appears to be possible to release stuck parts that are contacted over small areas such as dimples. The wear resistance of selectively coated W parts has been shown to be significantly improved on microengine test structures.
Two major problems associated with Si-based MEMS devices are stiction and wear. Surface modifications are needed to reduce both adhesion and friction in micromechanical structures to solve these problems. In this paper, the authors will present a process used to selectively coat MEMS devices with tungsten using a CVD (Chemical Vapor Deposition) process. The selective W deposition process results in a very conformal coating and can potentially solve both stiction and wear problems confronting MEMS processing. The selective deposition of tungsten is accomplished through silicon reduction of WF{sub 6}, which results in a self-limiting reaction. The selective deposition of W only on polysilicon surfaces prevents electrical shorts. Further, the self-limiting nature of this selective W deposition process ensures the consistency necessary for process control. Selective tungsten is deposited after the removal of the sacrificial oxides to minimize process integration problems. This tungsten coating adheres well and is hard and conducting, requirements for device performance. Furthermore, since the deposited tungsten infiltrates under adhered silicon parts and the volume of W deposited is less than the amount of Si consumed, it appears to be possible to release stuck parts that are contacted over small areas such as dimples. Results from tungsten deposition on MEMS structures with dimples will be presented. The effect of wet and vapor phase cleanings prior to the deposition will be discussed along with other process details. The W coating improved wear by orders of magnitude compared to uncoated parts. Tungsten CVD is used in the integrated-circuit industry, which makes this approach manufacturable.
Resonance Tunneling Diodes (RTDs) are devices that can demonstrate very high-speed operation. Typically they have been fabricated using epitaxial techniques and materials not consistent with standard commercial integrated circuits. The authors report here the first demonstration of SiO{sub 2}-Si-SiO{sub 2} RTDs. These new structures were fabricated using novel combinations of silicon integrated circuit processes.
Two major problems associated with Si-based MEMS (MicroElectroMechanical Systems) devices are stiction and wear. Surface modifications are needed to reduce both adhesion and friction in micromechanical structures to solve these problems. In this paper, the authors present a CVD (Chemical Vapor Deposition) process that selectively coats MEMS devices with tungsten and significantly enhances device durability. Tungsten CVD is used in the integrated-circuit industry, which makes this approach manufacturable. This selective deposition process results in a very conformal coating and can potentially address both stiction and wear problems confronting MEMS processing. The selective deposition of tungsten is accomplished through the silicon reduction of WF{sub 6}. The self-limiting nature of the process ensures consistent process control. The tungsten is deposited after the removal of the sacrificial oxides to minimize stress and process integration problems. The tungsten coating adheres well and is hard and conducting, which enhances performance for numerous devices. Furthermore, since the deposited tungsten infiltrates under adhered silicon parts and the volume of W deposited is less than the amount of Si consumed, it appears to be possible to release adhered parts that are contacted over small areas such as dimples. The wear resistance of tungsten coated parts has been shown to be significantly improved by microengine test structures.
An overview is given on the current status of three-dimensional (3D) photonic crystals. The realization of new 3d photonic crystal structures, the creation of high Q microcavities and the building of waveguide bends are presented. These devices form the basic building blocks for applications in signal processing and low threshold lasers.
Three-dimensional photonic lattices are engineered 'materials' which are the photonic analogues of semiconductors. These structures were first proposed and demonstrated in the mid-to-late 1980's. However, due to fabrication difficulties, lattices active in the infrared are only just emerging. Wide ranges of structures and fabrication approaches have been investigated. The most promising approach for many potential applications is a diamond-like structure fabricated using silicon microprocessing techniques. This approach has enabled the fabrication of 3-D silicon photonic lattices active in the infrared. The structures display band gaps centered from 12μ down to 1.55μ.
This process combines the best features of bulk and surface micromachining. It enables the production of stress free, thick, virtually arbitrarily shaped structures with well defined, thick or thin sacrificial layers, high sacrificial layer selectivity and large undercuts using IC compatible, processes. The basis of this approach is the use of readily available {111} oriented substrates, anisotropic Si trench etching, SiN masking and KOH etching.
Silicon processing techniques were used to fabricate 3-D photonic lattices with band gaps in the infrared. The demonstration vehicle was a selective infrared mirror/band pass filter, a wide range of other applications are also possible.
Interconnect delays, arising in part from intralevel capacitance, are one of the factors limiting the performance of advanced circuits. In addition, the problem of filling the spaces between neighboring metal lines with an insulator is becoming increasingly acute as aspect ratios increase. We address these problems simultaneously by intentionally creating an air gap between closely spaced metal lines. Undesirable topography is eliminated using a spin-on dielectric. We then cap the wafers with silicon dioxide and planarize using chemical mechanical polishing. Simple modeling of test structures predicts an equivalent dielectric constant of 1.9 on features similar to those expected for 0.25 micron technologies. Two level metal test structures fabricated in a 0.5 micron CMOS technology show that the process can be readily integrated with current standard CMOS processes. The potential problems of via misalignment, overall dielectric stack height, and the relative difficulty of ensuring void formation compared to that of ensuring a void-free fill are considered.
In this work, the authors have applied mold micromachining and standard photolithographic techniques to the fabrication of parts integrated with 0.4 micron pitch diffraction gratings. In principle, the approach should be scaleable to considerably finer pitches. They have achieved this by relying on the thickness of deposited or grown films, instead of photolithography, to determine the grating pitch. The gratings can be made to extend over large areas and the entire process is compatible with batch processing. Literally thousands of parts can be batch fabricated from a single lot of six inch wafers. In the first stage of the process they fabricate a planarized silicon dioxide pad over which the silicon nitride wave guide runs. The grating is formed by first patterning and etching single crystalline silicon to form a series of trenches with well defined pitch. The silicon bounding the trenches is then thinned by thermal oxidation followed by stripping of the silicon dioxide. The trenches are filled by a combination of polysilicon depositions and thermal oxidations. Chemical mechanical polishing (CMP) is used to polish back these structures resulting in a series of alternating 2000 {angstrom} wide lines of silicon and silicon dioxide. The thickness of the lines is determined by the oxidation time and the polysilicon deposition thickness. The silicon lines are selectively recessed by anisotropic reactive ion etching, thus forming the mold for the grating. The mold is filled with low stress silicon nitride deposited by chemical vapor deposition. A wave guide is then patterned into the silicon nitride and the mold is locally removed by a combination of deep silicon trench etching and wet KOH etching. This results in a suspended diffraction grating/membrane over the KOH generated pit.
Interconnect delays, arising in part from intralevel capacitance, are one of the limiting factors in the performance of advanced integrated circuits. In addition, the problem of filling the spaces between neighboring metal lines with an insulator is becoming increasingly severe as aspect ratios increase. We address these problems by intentionally creating a air gap between closely spaced metal lines. The ends of the air gap and reentrant features are then sealed using a spin on dielectric. The entire structure is then capped with silicon dioxide and planarized . Simple modeling of mechanical test structures on silicon predicts an equivalent dielectric constant of 1.9 on features similar to those expected for 0.25 micron technologies. Metal to metal test structures fabricated in a 0.5 micron CMOS technology show that the process can be readily integrated with chemical mechanical polishing and current standard CMOS processes.
A range of different ternary refractory nitride compositions have been deposited by CVD (chemical vapor deposition) for the systems TiSiN, WBN, and WSiN. The precursors used are readily available. The structure, electrical, and barrier properties of the films produced by CVD are similar to those observed for films with similar compositions deposited by PVD (physical vapor deposition). The step coverage of the CVD processes developed is good and in some cases, exceptional. A combination of desirable resistivity, step coverage, and barrier properties exists simultaneously over a reasonable range of compositions for each system. Initial attempts to integrate WSiN films into a standard 0.5 micrometer CMOS process flow in place of a sputtered Ti/TiN stack were successful.
The authors have used chemical vapor deposition to grow ternary tungsten-based diffusion barriers to determine if they exhibit properties similar to those of sputter-deposited ternaries. A range of different W-B-N compositions in a band of compositions roughly between 20 and 40% W were produced. The deposition temperature was low, 350 C, and the precursors used are well accepted by the industry. Deposition rates are high for a diffusion barrier application. Resistivities range from 200 to 20,000 {micro}{Omega}-cm, the films with the best barrier properties having {approximately}1,000 {micro}{Omega}-cm resistivities. Adhesion to oxides is sufficient to allow these films to be used as the adhesion layer in a tungsten chemical mechanical polishing plug application. The films are x-ray amorphous as-deposited and have crystallization temperatures of up to 900 C. Barrier performance against Cu has been tested using diode test structures. A composition of W{sub .23}B{sub .49}N{sub .28} was able to prevent diode failure up to a 700 C, 30 minute anneal. These materials, deposited by CVD, display properties similar to those deposited by physical deposition techniques.
Bulk micromachining generally refers to processes involving wet chemical etching of structures formed out of the silicon substrate and so is limited to fairly large, crude structures. Surface micromachining allows intricate patterning of thin films of polysilicon and other materials to form essentially two-dimensional layered parts (since the thickness of the parts is limited by the thickness of the deposited films). There is a third type of micromachining in which the part is formed by filling a mold which was defined by photolithographic means. Historically micromachining molds have been formed in some sort of photopolymer, be it with x-ray lithography (``LIGA``) or more conventional UV lithography, with the aim of producing piece parts. Recently, however, several groups including ours at Sandia have independently come up with the idea of forming the mold for mechanical parts by etching into the silicon substrate itself. In Sandia`s mold process, the mold is recessed into the substrate using a deep silicon trench etch, lined with a sacrificial or etch-stop layer, and then filled with any of a number of mechanical materials. The completed structures are not ejected from the mold to be used as piece parts rather, the mold is dissolved from around selected movable segments of the parts, leaving the parts anchored to the substrate. Since the mold is recessed into the substrate, the whole micromechanical structure can be formed, planarized, and integrated with standard silicon microelectronic circuits before the release etch. In addition, unlike surface-micromachined parts, the thickness of the molded parts is limited by the depth of the trench etch (typically 10--50 {mu}m) rather than the thickness of deposited polysilicon (typically 2 {mu}m). The capability of fabricating thicker (and therefore much stiffer and more massive) parts is critical for motion-sensing structures involving large gimballed platforms, proof masses, etc.
Functioning, matrixed, field emission devices have been fabricated using a modification of standard integrated circuit fabrication techniques. The emitter-to-gate spacing is fixed by the thickness of a deposited oxide and not by photolithographic techniques. Modeling of the emitted electron trajectories using a two dimensional, Poisson solver, finite difference code indicates that much of the current runs perpendicular to plane of the part. Functioning triode structures have been fabricated using this approach. Emission current, to a collector electrically and physically separated from the matrixed array follows Fowler-Nordheim behavior.
We report on the use of a deposition/etch approach to the loss of selectivity problem, using high activity fluorine chemistries in the etch step. Proof-of-concept experiments were initially performed in a hot wall system, the excellent results obtained lead us to prove out the concept in a commercially available cold wall Genus reactor. We observed that WF{sub 6} is ineffective as an etchant of W. The technique has been able to produce perfectly selective depositions 1 micron thick in both hot wall, and cold wall, systems. Sheet resistivity values and film morphology are good. 9 refs., 4 figs., 1 tab.