Publications

Abstract not provided.

The burgeoning new technology of Micro-Electro-Mechanical Systems (MEMS) shows great promise in the weapons arena. We can now conceive of micro-gyros, micro-surety systems, and micro-navigators that are extremely small and inexpensive. Do we want to use this new technology in critical applications such as nuclear weapons? This question drove us to understand the reliability and failure mechanisms of silicon surface-micromachined MEMS. Development of a testing infrastructure was a crucial step to perform reliability experiments on MEMS devices and will be reported here. In addition, reliability test structures have been designed and characterized. Many experiments were performed to investigate failure modes and specifically those in different environments (humidity, temperature, shock, vibration, and storage). A predictive reliability model for wear of rubbing surfaces in microengines was developed. The root causes of failure for operating and non-operating MEMS are discussed. The major failure mechanism for operating MEMS was wear of the polysilicon rubbing surfaces. Reliability design rules for future MEMS devices are established.

Two major problems associated with Si-based MEMS (MicroElectroMechanical Systems) devices are stiction and wear. Surface modifications are needed to reduce both adhesion and friction in micromechanical structures to solve these problems. In this paper, we will present a CVD (Chemical Vapor Deposition) process that selectively coats MEMS devices with tungsten and significantly enhances device durability. Tungsten CVD is used in the integrated-circuit industry, which makes this approach manufacturable. This selective deposition process results in a very conformal coating and can potentially address both stiction and wear problems confronting MEMS processing. The selective deposition of tungsten is accomplished through the silicon reduction of WF6. The self-limiting nature of the process ensures consistent process control. The tungsten is deposited after the removal of the sacrificial oxides to minimize stress and process integration problems. The tungsten coating adheres well and is hard and conducting, which enhances performance for numerous devices. Furthermore, since the deposited tungsten infiltrates under adhered silicon parts and the volume of W deposited is less than the amount of Si consumed, it appears to be possible to release adhered parts that are contacted over small areas such as dimples. The wear resistance of tungsten coated parts has been shown to be significantly improved by microengine test structures.

Microelectromechanical Systems (MEMS) packaging is much different from conventional integrated circuit (IC) packaging. Many MEMS devices must interface to the environment in order to perform their intended function, and the package must be able to facilitate access with the environment while protecting the device. The package must also not interfere with or impede the operation of the MEMS device. The die attachment material should be low stress, and low outgassing, while also minimizing stress relaxation overtime which can lead to scale factor shifts in sensor devices. The fabrication processes used in creating the devices must be compatible with each other, and not result in damage to the devices. Many devices are application specific requiring custom packages that are not commercially available. Devices may also need media compatible packages that can protect the devices from harsh environments in which the MEMS device may operate. Techniques are being developed to handle, process, and package the devices such that high yields of functional packaged parts will result. Currently, many of the processing steps are potentially harmful to MEMS devices and negatively affect yield. It is the objective of this paper to review and discuss packaging challenges that exist for MEMS systems and to expose these issues to new audiences from the integrated circuit packaging community.

Manufacturers widely recognize testing as a major factor in the cost, producability, and delivery of product in the $100 billion integrated circuit business: {open_quotes}The rapid development of VLSI using sub-micron CMOS technology has suddenly exposed traditional test techniques as a major cost factor that could restrict the development of VLSI devices exceeding 512 pins an operating frequencies above 200 MHz.{close_quotes} -- 1994 Semiconductor Industry Association Roadmap, Design and Test, Summary, pg. 43. This problem increases dramatically for stockpile electronics, where small production quantities make it difficult to amortize the cost of increasingly expensive testers. Application of multiple ICs in Multi-Chip Modules (MCM) greatly multiplies testing problems for commercial and defense users alike. By traditional test methods, each new design requires custom test hardware and software and often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems limit capabilities in testing at-speed (>200 MHz), high-impedance, and high-accuracy analog signals. This project proposed a revolutionary approach to these problems: replace the multi-million dollar external test system with an inexpensive test system integrated onto the product wafer. Such a methodology enables testing functions otherwise unachievable by conventional means, particularly in the areas of high-frequency, at-speed testing, high impedance analog circuits, and known good die assessment. The techniques apply specifically to low volume applications, typical of Defense Programs, where testing costs represent an unusually high proportional of product costs, not easily amortized.

Any advance beyond the density of standard 2D Multichip Modules (MCM) will require a vertical interconnect technology that can produce reliable area array interconnection with small feature sizes. Laser drilled vertical vias have been controllably produced in standard silicon (Si) wafers down to 0.035mm (0.0014 inches) in diameter. Several laser systems and their system parameters have been explored to determine the optimum parametric set for repeatable vias in Si. The vias produced have exhibited clean smooth interior surfaces with an aspect ratio of up to 20:1 with little or no taper. All laser systems used, their system parameters, design modifications, theory of operation, and drilling results are discussed.