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IEEE Transactions on Nuclear Science
Black, Jeffrey B. ; Dame, Jeff A.; Black, Dolores A. ; Dodd, Paul E. ; Shaneyfelt, Marty R. ; Teifel, John T. ; Salas, Joseph G. ; Steinbach, Robert; Davis, Matthew; Reed, Robert A.; Weller, Robert A.; Trippe, James M. ; Warren, Kevin M.; Tonigan, Andrew M.; Schrimpf, Ronald D.; Marquez, Richard S.
Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.
IEEE Transactions on Nuclear Science
Black, Jeffrey B. ; Dame, Jeff A.; Black, Dolores A. ; Dodd, Paul E. ; Shaneyfelt, Marty R. ; Teifel, John T. ; Salas, Joseph G. ; Steinbach, Robert; Davis, Matthew; Reed, Robert A.; Weller, Robert A.; Trippe, James M. ; Warren, Kevin M.; Tonigan, Andrew M.; Schrimpf, Ronald D.; Marquez, Richard S.
Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.
Teifel, John T. ; Wang, Cheng C.
Teifel, John T. ; Wang, Cheng C.
Teifel, John T. ; Black, Jeffrey B. ; Cavanaugh, William S. ; Clark, Kevin; McCasland, Jeffrey T. ; Owen, Richard E. ; Sharif, Moslema S.
Teifel, John T.
Teifel, John T. ; Black, Jeffrey B. ; Cavanaugh, William S. ; Clark, Kevin D. ; McCasland, Jeffrey T. ; Owen, Richard E. ; Sharif, Moslema S.
Teifel, John T. ; Land, Matthew L. ; Miller, Russell D.
Teifel, John T. ; Land, Matthew L. ; Miller, Russell D.
Black, Jeffrey B. ; Dodds, Nathaniel A. ; Dodd, Paul E. ; Shaneyfelt, Marty R. ; Martinez, Marino M. ; Teifel, John T. ; Pearson, Sean P. ; Ma, Kwok-Kee M.
Teifel, John T. ; Black, Jeffrey B. ; Edwards, Eric E. ; Mannos, Tom M.
Teifel, John T. ; Black, Jeffrey B. ; Edwards, Eric E. ; Mannos, Tom M.
Teifel, John T. ; Flores, Richard S. ; Pearson, Sean P. ; Nowlin, Robert N. ; Black, Jeffrey B.
Proceedings - Electronic Components and Technology Conference
Teifel, John T. ; Flores, Richard S. ; Jarecki, Robert L. ; Bauer, Todd B. ; Shinde, Subhash L.
Teifel, John T. ; Flores, Richard S. ; Jarecki, Robert L. ; Bauer, Todd B. ; Shinde, Subhash L.
Teifel, John T. ; Flores, Richard S. ; Pearson, Sean P. ; Begay, Cynthia B. ; Palmer, Jeremy A.
Teifel, John T. ; Flores, Richard S. ; Pearson, Sean P. ; Begay, Cynthia B. ; Ma, Kwok-Kee M. ; Palmer, Jeremy A.
Teifel, John T. ; Flores, Richard S. ; Pearson, Sean P. ; Begay, Cynthia B. ; Ma, Kwok-Kee M. ; Palmer, Jeremy A.
Ma, Kwok-Kee M. ; Teifel, John T. ; Flores, Richard S.
Ma, Kwok-Kee M. ; Teifel, John T. ; Flores, Richard S.
Teifel, John T. ; Flores, Richard S. ; Pearson, Sean P. ; Begay, Cynthia B. ; Ma, Kwok-Kee M.
IEEE Transactions on Nuclear Science
Teifel, John T.
Dual-modular-redundancy (DMR) architectures use duplication and self-voting asynchronous circuits to mitigate single event transients (SETs). The area and performance of DMR circuitry is evaluated against conventional triple-modular-redundancy (TMR) logic. Benchmark ASIC circuits designed with DMR logic show a 1024% area improvement for flip-flop designs, and a 33% improvement for latch designs. © 2006 IEEE.
Teifel, John T.
Proceedings - International Carnahan Conference on Security Technology
Teifel, John T.
Asynchronous integrated circuit technology provides low-power and low-noise operation for portable electronic security applications. Rather than using a global clock, asynchronous circuits employ a system of distributed handshake signals that control on-chip dataflow; reducing power consumption to only those parts of a chip actively involved in computation. Sandia has developed an automated asynchronous design flow that enables the rapid development of these asynchronous ASICs. This paper describes the design of asynchronous DES encryption circuits using this flow, and evaluates their performance against standard synchronous implementations. © 2006 IEEE.
Teifel, John T.
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