Process variations within Field Programmable Gate Arrays (FPGAs) provide a rich source of entropy and are therefore well-suited for the implementation of Physical Unclonable Functions (PUFs). However, careful considerations must be given to the design of the PUF architecture as a means of avoiding undesirable localized bias effects that adversely impact randomness, an important statistical quality characteristic of a PUF. Here in this paper, we investigate a ring-oscillator (RO) PUF that leverages localized entropy from individual look-up table (LUT) primitives. A novel RO construction is presented that enables the individual paths through the LUT primitive to be measured and isolated at high precision, and an analysis is presented that demonstrates significant levels of localized design bias. The analysis demonstrates that delay-based PUFs that utilize LUTs as a source of entropy should avoid using FPGA primitives that are localized to specific regions of the FPGA, and instead, a more robust PUF architecture can be constructed by distributing path delay components over a wider region of the FPGA fabric. Compact RO PUF architectures that utilize multiple configurations within a small group of LUTs are particularly susceptible to these types of design-level bias effects. The analysis is carried out on data collected from a set of identically designed, hard macro instantiations of the RO implemented on 30 copies of a Zynq 7010 SoC.
Earth and Space 2022: Space Exploration, Utilization, Engineering, and Construction in Extreme Environments - Selected Papers from the 18th Biennial International Conference on Engineering, Science, Construction, and Operations in Challenging Environments
Analysis of radiation effects on electrical circuits requires computationally efficient compact radiation models. Currently, development of such models is dominated by analytic techniques that rely on empirical assumptions and physical approximations to render the governing equations solvable in closed form. In this paper we demonstrate an alternative numerical approach for the development of a compact delayed photocurrent model for a pn-junction device. Our approach combines a system identification step with a projection-based model order reduction step to obtain a small discrete time dynamical system describing the dynamics of the excess carriers in the device. Application of the model amounts to a few small matrix-vector multiplications having minimal computational cost. We demonstrate the model using a radiation pulse test for a synthetic pn-junction device.
Compact semiconductor device models are essential for efficiently designing and analyzing large circuits. However, traditional compact model development requires a large amount of manual effort and can span many years. Moreover, inclusion of new physics (e.g., radiation effects) into an existing model is not trivial and may require redevelopment from scratch. Machine Learning (ML) techniques have the potential to automate and significantly speed up the development of compact models. In addition, ML provides a range of modeling options that can be used to develop hierarchies of compact models tailored to specific circuit design stages. In this paper, we explore three such options: (1) table-based interpolation, (2) Generalized Moving Least-Squares, and (3) feed-forward Deep Neural Networks, to develop compact models for a p-n junction diode. We evaluate the performance of these “data-driven” compact models by (1) comparing their voltage-current characteristics against laboratory data, and (2) building a bridge rectifier circuit using these devices, predicting the circuit's behavior using SPICE-like circuit simulations, and then comparing these predictions against laboratory measurements of the same circuit.
Compact semiconductor device models are essential for efficiently designing and analyzing large circuits. However, traditional compact model development requires a large amount of manual effort and can span many years. Moreover, inclusion of new physics (e.g., radiation effects) into an existing model is not trivial and may require redevelopment from scratch. Machine Learning (ML) techniques have the potential to automate and significantly speed up the development of compact models. In addition, ML provides a range of modeling options that can be used to develop hierarchies of compact models tailored to specific circuit design stages. In this paper, we explore three such options: (1) table-based interpolation, (2) Generalized Moving Least-Squares, and (3) feedforward Deep Neural Networks, to develop compact models for a p-n junction diode. We evaluate the performance of these "data-driven" compact models by (1) comparing their voltage-current characteristics against laboratory data, and (2) building a bridge rectifier circuit using these devices, predicting the circuit's behavior using SPICE-like circuit simulations, and then comparing these predictions against laboratory measurements of the same circuit.
We present a new, non-destructive electrical technique, Power Spectrum Analysis (PSA). PSA as described here uses off-normal biasing, an unconventional way of powering microelectronics devices. PSA with off-normal biasing can be used to detect subtle differences between microelectronic devices. These differences, in many cases, cannot be detected by conventional electrical testing. In this paper, we highlight PSA applications related to aging and counterfeit detection.
We present a new, non-destructive electrical technique, Power Spectrum Analysis (PSA). PSA as described here uses off-normal biasing, an unconventional way of powering microelectronics devices. PSA with off-normal biasing can be used to detect subtle differences between microelectronic devices. These differences, in many cases, cannot be detected by conventional electrical testing. In this paper, we highlight PSA applications related to aging and counterfeit detection.