Representing complex systems as graphs enables use of mathematical tools to identify faults or predict failures. Graph nodes correspond to individual modules or subsystems, and edges link coupled system parts. ‘Probes’ measure the node outputs, monitoring the system health for unexpected behavior. Assuming one cannot probe every point, within a system, the fault correlates to a region—not necessarily the specific location. Bayesian networks trained to understand fault patterns can accurately identify the source. The diagnostic tool described aides debugging by pinpointing system failure causes. For predictive maintenance, probe data develop probability distribution functions describing subsystem mean time to failure. Unit lifetime can be estimated through these probability distributions. Two approaches include using Bayesian classifiers to infer the system failure source and developing maintenance schedules by treating systems as collections of random variables. When failure behavior does not follow a closed form function, use of similarity models is proposed.
During the development of high-consequence items, test systems should be capable of differenti ating between test failures resulting from narrowly missing requirements versus those indicating potentially catastrophic faults. In many instances, classifying the data corresponds to simply identifying whether measured waveforms have approximately the anticipated shape. Cast in this light, the problem reduces to converting raw data into a form optimal for use with neural network classifiers. This manuscript investigates different means of representing raw data for image classification. Raw data plots and Short Time Fourier Transform (STFT) spectrograms are classified by both custom built, small-scale, Convolution Neural Networks (CNN) and open-source, multi-million parameter, pre-trained deep CNNs. In the case of time varying frequency content, the STFTs provide images with greater detail and can be accurately classified with simpler networks. This requires less mem ory and runs faster than classifying the raw data using the more sophisticated options—making STFTs optimal for applications with memory constraints. STFTs are not a panacea. In some cases the time-domain signal contains useful information that should not be discarded. Rather than using raw data or STFTs, the images can be constructed from both by using red and green channels of an RGB image to visualize the real and imaginary components of the transform, with the raw data occupying the blue channel.
Hardware-in-the-Loop (HIL) methodologies for test system development often require simulations capable of running at MHz speeds on FPGAs. The stringent memory and speed constraints necessitate compromises between model fidelity and execution speed. Numerically solving the underlying governing equations represents the highest accuracy, but slowest responding approach. By storing pre-determined results in look-up-tables (LUT), one can balance speed and accuracy.
Hardware in the Loop (HIL) testing methodologies have become widespread in industry. Typically, they focus on developing control algorithms for systems such as autonomous vehicles or aircraft. An oft overlooked aspect of product development is the design and fabrication of a test system for validating that the product meets requirements. Abstractly, a test system differs little from a control system—testers provide signals to the unit, monitor feedback, and base decisions on the results. While the time scales may differ, the functionalities are conceptually similar. Viewed in this light, it becomes natural to extend HIL approaches to tester development. By replacing a physical unit with a proxy model deployed to a real-time or pseudo real-time target, test systems can be developed in parallel with the design and fabrication of a first production unit. This saves considerable time in the life cycle from conceptual design to realized product. This manuscript demonstrates the process flow using a capacitive discharge unit as an exemplar.
This report demonstrates that applying graph theory techniques provides a way to obtain sufficient statistics in finding errors when testing complex state machines. It discusses how to define the tests, then demonstrates how to automatically generate test suites that diversify test cases, subject to constraints. If included within a continuous integration approach, these constructs provide an unbiased means to systematically check for errors within the latest controller software release.
Electrical conduction in silica-based capacitors under a combined effect of intermediate electric field and temperature (2.5 - 10 kV/mm, 50-300°C) is dominated by localized motion of high mobility ions such as sodium. Thermally stimulated polarization and depolarization current (TSPC/TSDC) characterization was carried out on poled fused silica and AF32 glass samples. Two relaxation mechanisms were found during the depolarization step and an anomalous response for the second TSDC peak was observed. Absorption current measurements were performed on the glass samples and a time-dependent response was observed when subjected to different electro-thermal conditions. It was found that at low temperature (T = 175 °C) and short times, the current follows a linear behavior (I α V) while at high temperature (T = 250 °C), the current follows V0.5. TSPC/TSDC and absorption current measurements results led to the conclusion that (1) Poole-Frenkel dominates conduction at high temperatures and at longer times and that (2) ionic blockage and/or H+/H3O+ injection are responsible for the observed anomalous current response.
The reports of 35 J/cc energy density in thinned alkali-free glasses make it a top candidate for next generation high energy density capacitors. In this article, we demonstrate a scalable process to take currently available commercial glass and fabricate fully packaged capacitors. These prototypes have 0.086 J/cc energy density at 1000 V, making them competitive with some commercially available ceramic capacitors. This was achieved while focusing on developing a process for thinning and handling the glass and without minimization of the inactive volume of the capacitor. These results portend the achievement of significantly higher energy densities in devices made from alkali-free glass.
Alkali-free glasses show immense promise for the development of high-energy density capacitors. The high breakdown strengths on single-layer sheets of glass suggest the potential for improved energy densities over existing state-of-the art polymer capacitors. In this paper, we demonstrate the ability to package thin glass to make solid-state capacitors. Individual layers are bonded using epoxy, leading to capacitors that exhibit stable operation over the temperature range -55 °C to +65 °C. This fabrication approach is scalable and allows for proof testing individual layers prior to incorporation of the stack, providing a blueprint for the fabrication of high-energy density capacitors.
Alkali-free glasses, which exhibit high energy storage densities (~35 J/cc), present a unique opportunity to couple high temperature stability with high breakdown strength, and thus provide an avenue for capacitor applications with stringent temperature and power requirements. Realizing the potential of these materials in kilovolt class capacitors with >1 J/cc recoverable energy density requires novel packaging strategies that incorporate these extremely fragile dielectrics. In this paper, we demonstrate the feasibility of fabricating wound capacitors using 50-μm-thick glass. Two capacitors were fabricated from 2.8-m-long ribbons of thin (50 μm) glass wound into 125-140-mm-diameter spools. The capacitors exhibit a capacitance of 70-75 nF with loss tangents below 1%. The wound capacitors can operate up to 1 kV and show excellent temperature stability to 150 °C. By improving the end terminations, the self-resonance can be shifted to above 1 MHz, indicating that these materials may be useful for pulsed power applications with microsecond discharge times.
