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Chronicles of astra: Challenges and lessons from the first petascale arm supercomputer

International Conference for High Performance Computing, Networking, Storage and Analysis, SC

Laros, James H.; Younge, Andrew J.; Hammond, Simon D.; Laros, James H.; Curry, Matthew J.; Aguilar, Michael J.; Hoekstra, Robert J.; Brightwell, Ronald B.

Arm processors have been explored in HPC for several years, however there has not yet been a demonstration of viability for supporting large-scale production workloads. In this paper, we offer a retrospective on the process of bringing up Astra, the first Petascale supercomputer based on 64-bit Arm processors, and validating its ability to run production HPC applications. Through this process several immature technology gaps were addressed, including software stack enablement, Linux bugs at scale, thermal management issues, power management capabilities, and advanced container support. From this experience, several lessons learned are formulated that contributed to the successful deployment of Astra. These insights can be helpful to accelerate deploying and maturing other first-seen HPC technologies. With Astra now supporting many users running a diverse set of production applications at multi-thousand node scales, we believe this constitutes strong supporting evidence that Arm is a viable technology for even the largest-scale supercomputer deployments.

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Quantum dots with split enhancement gate tunnel barrier control

Applied Physics Letters

Rochette, S.; Rudolph, Martin R.; Roy, A.M.; Curry, Matthew J.; Eyck, G.A.T.; Manginell, Ronald P.; Wendt, J.R.; Pluym, Tammy P.; Carr, Stephen M.; Ward, Daniel R.; Lilly, M.P.; Carroll, Malcolm

We introduce a silicon metal-oxide-semiconductor quantum dot architecture based on a single polysilicon gate stack. The elementary structure consists of two enhancement gates separated spatially by a gap, one gate forming a reservoir and the other a quantum dot. We demonstrate that, in three devices based on two different versions of this elementary structure, a wide range of tunnel rates is attainable while maintaining single-electron occupation. A characteristic change in the slope of the charge transitions as a function of the reservoir gate voltage, attributed to screening from charges in the reservoir, is observed in all devices and is expected to play a role in the sizable tuning orthogonality of the split enhancement gate structure. The all-silicon process is expected to minimize strain gradients from electrode thermal mismatch, while the single gate layer should avoid issues related to overlayers (e.g., additional dielectric charge noise) and help improve the yield. Finally, reservoir gate control of the tunnel barrier has implications for initialization, manipulation, and readout schemes in multi-quantum dot architectures.

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Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

Physical Review Applied

Carroll, Malcolm; Rochette, Sophie; Rudolph, Martin R.; Roy, A.M.; Curry, Matthew J.; Ten Eyck, Gregory A.; Manginell, Ronald P.; Wendt, J.R.; Pluym, Tammy P.; Carr, Stephen M.; Ward, Daniel R.; Lilly, Michael L.; Pioro-Ladriere, Michel

We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down to the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.

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Results 1–25 of 29
Results 1–25 of 29