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Single Event Upset and Total Ionizing Dose Response of 12LP FinFET Digital Circuits

Spear, Matthew; Wallace, Trace; Wilson, Donald; Solano, Jose; Irumva, Gedeon; Esqueda, Ivan S.; Barnaby, Hugh J.; Clark, Lawrence T.; Brunhaver, John; Turowski, Marek; Mikkola, Esko; Hughart, David R.; Young, Joshua M.; Manuel, Jack E.; Agarwal, Sapan A.; Vaandrager, Bastiaan L.; Vizkelethy, Gyorgy V.; King, Michael P.; Marinella, Matthew J.

Abstract not provided.

Single Event Upset and Total Ionizing Dose Response of 12LP FinFET Digital Circuits

Spear, Matthew; Wallace, Trace; Wilson, Donald; Solano, Jose; Irumva, Gedeon; Esqueda, Ivan S.; Barnaby, Hugh J.; Clark, Lawrence T.; Brunhaver, John; Turowski, Marek; Mikkola, Esko; Hughart, David R.; Young, Joshua M.; Manuel, Jack E.; Agarwal, Sapan A.; Vaandrager, Bastiaan L.; Vizkelethy, Gyorgy V.; Gutierrez, Amos; Trippe, James M.; King, Michael P.; Bielejec, Edward S.; Marinella, Matthew J.

Abstract not provided.

Self-correcting Flip-flops for Triple Modular Redundant Logic in a 12-nm Technology

Proceedings - IEEE International Symposium on Circuits and Systems

Clark, Lawrence T.; Duvnjak, Alen; Young-Sciortino, Clifford; Cannon, Matthew J.; Brunhaver, John; Agarwal, Sapan A.; Wilson, Donald; Barnaby, Hugh; Marinella, Matthew J.

Area efficient self-correcting flip-flops for use with triple modular redundant (TMR) soft-error hardened logic are implemented in a 12-nm finFET process technology. The TMR flip-flop slave latches self-correct in the clock low phase using Muller C-elements in the latch feedback. These C-elements are driven by the two redundant stored values and not by the slave latch itself, saving area over a similar implementation using majority gate feedback. These flip-flops are implemented as large shift-register arrays on a test chip and have been experimentally tested for their soft-error mitigation in static and dynamic modes of operation using heavy ions and protons. We show how high clock skew can result in susceptibility to soft-errors in the dynamic mode, and explain the potential failure mechanism.

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Analog Neural Network Inference Accuracy in One-Selector One-Resistor Memory Arrays

Proceedings - 2022 IEEE International Conference on Rebooting Computing, ICRC 2022

Xiao, Tianyao X.; Bennett, Christopher H.; Wilson, Donald; Feinberg, Benjamin F.; Agarwal, Sapan A.; Marinella, Matthew J.

Non-volatile memory arrays require select devices to ensure accurate programming. The one-selector one-resistor (1S1R) array where a two-terminal nonlinear select device is placed in series with a resistive memory element is attractive due to its high-density data storage; however, the effect of the nonlinear select device on the accuracy of analog in-memory computing has not been explored. This work evaluates the impact of select and memory device properties on the results of analog matrix-vector multiplications. We integrate nonlinear circuit simulations into CrossSim and perform end-to-end neural network inference simulations to study how the select device affects the accuracy of neural network inference. We propose an adjustment to the input voltage that can effectively compensate for the electrical load of the select device. Our results show that for deep residual networks trained on CIFAR-10, a compensation that is uniform across all devices in the system can mitigate these effects over a wide range of values for the select device I-V steepness and memory device On/Off ratio. A realistic I-V curve steepness of 60 mV/dec can yield an accuracy on CIFAR-10 that is within 0.44% of the floating-point accuracy.

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6 Results
6 Results