It is shown that final chip passivation layers can have a significant impact on total dose hardness. A number of final chip passivation layers are evaluated to identify films that mitigate enhanced low-dose-rate sensitivity (ELDRS) in National Semiconductor Corporation's linear bipolar technologies. It is shown that devices fabricated with either a low temperature oxide or a tetraethyl ortho silicate passivation do not exhibit significant ELDRS effects up to 100 krad(SiO{sub 2}). Passivation studies on CMOS SRAMs suggest that it is unlikely that the passivation layers (or processing tools) are acting as a new source of hydrogen, which could drift or diffuse into the oxide and increase ELDRS sensitivity. Instead, it is possible that the passivation layers affect the mechanical stress in the oxide, which may affect oxide trap properties and possibly the release and mobility of hydrogen. Correlations between mechanical stress induced by the passivation layers and radiation degradation are discussed.
Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.
The effects of photocurrents in nuclear weapons induced by proximal nuclear detonations are well known and remain a serious hostile environment threat for the US stockpile. This report describes the final results of an LDRD study of the physical phenomena underlying prompt photocurrents in microelectronic devices and circuits. The goals of this project were to obtain an improved understanding of these phenomena, and to incorporate improved models of photocurrent effects into simulation codes to assist designers in meeting hostile radiation requirements with minimum build and test cycles. We have also developed a new capability on the ion microbeam accelerator in Sandia's Ion Beam Materials Research Laboratory (the Transient Radiation Microscope, or TRM) to supply ionizing radiation in selected micro-regions of a device. The dose rates achieved in this new facility approach those possible with conventional large-scale dose-rate sources at Sandia such as HERMES III and Saturn. It is now possible to test the physics and models in device physics simulators such as Davinci in ways not previously possible. We found that the physical models in Davinci are well suited to calculating prompt photocurrents in microelectronic devices, and that the TRM can reproduce results from conventional large-scale dose-rate sources in devices where the charge-collection depth is less than the range of the ions used in the TRM.
Improvements have been made at TRIUMF to permit higher proton intensities of up to 1010 cm-2s-1 over the energy range 20-500 MeV. This improved capability enables the study of displacement damage effects that require higher fluence irradiations. In addition, a high energy neutron irradiation capability has been developed for terrestrial cosmic ray soft error rate (SER) characterization of integrated circuits. The neutron beam characteristics of this facility are similar to those currently available at the Los Alamos National Laboratory WNR test facility. SER data measured on several SRAMs using the TRIUMF neutron beam are in good agreement with the results obtained on the same devices using the WNR facility. The TRIUMF neutron beam also contains thermal neutrons that can be easily removed by a sheet of cadmium. The ability to choose whether thermal neurons are present is a useful attribute not possible at the WNR.
High-energy ion-irradiated 3.3-nm oxynitride film and 2.2-nm SiO2-film MOS capacitors show premature break-down during subsequent electrical stress. This degradation in breakdown increases with increasing ion linear energy transfer (LET), increasing ion fluence, and decreasing oxide thickness. The reliability degradation due to high-energy ion-induced latent defects is explained by a simple percolation model of conduction through SiO2 layers with irradiation and/or electrical stress-induced defects. Monitoring the gate-leakage current reveals the presence of latent defects in the dielectric films. These results may be significant to future single-event effects and single-event gate rupture tests for MOS devices and ICs with ultrathin gate oxides.
The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-Dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMS, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMS is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.
Under this effort, a new method for studying the single event upset (SEU) in microelectronics has been developed and demonstrated. Called TRIBICC, for Time Resolved Ion Beam Induced Charge Collection, this technique measures the transient charge-collection waveform from a single heavy-ion strike with a {minus}.03db bandwidth of 5 GHz. Bandwidth can be expanded up to 15 GHz (with 5 ps sampling windows) by using an FFT-based off-line waveform renormalization technique developed at Sandia. The theoretical time resolution of the digitized waveform is 24 ps with data re-normalization and 70 ps without re-normalization. To preserve the high bandwidth from IC to the digitizing oscilloscope, individual test structures are assembled in custom high-frequency fixtures. A leading-edge digitized waveform is stored with the corresponding ion beam position at each point in a two-dimensional raster scan. The resulting data cube contains a spatial charge distribution map of up to 4,096 traces of charge (Q) collected as a function of time. These two dimensional traces of Q(t) can cover a period as short as 5 ns with up to 1,024 points per trace. This tool overcomes limitations observed in previous multi-shot techniques due to the displacement damage effects of multiple ion strikes that changed the signal of interest during its measurement. This system is the first demonstration of a single-ion transient measurement capability coupled with spatial mapping of fast transients.
SEU is studied in SOI transistors and circuits with various body tie structures. The importance of impact ionization effects, including single-event snapback, is explored. Implications for hardness assurance testing of SOI integrated circuits are discussed.
Large differences in charge buildup in SOI buried oxides can result between x-ray and Co-60 irradiations. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored.
Scanning capacitance microscopy (SCM) was used to study the cross section of an operating p-channel MOSFET. We discuss the novel test structure design and the modifications to the SCM hardware that enabled us to perform SCM while applying dc bias voltages to operate the device. The results are compared with device simulations performed with DAVINCI.
Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it is likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance.
Floating body effects can undermine the soft-error tolerance of partially-depleted SOI technologies [1, 2]. Body ties are used to mitigate floating body effects [3,4]. In this paper, we study the charge collection properties and effectiveness of different body tie designs for reducing soft errors induced by energetic particle strikes.
The basic mechanisms of single-event upset are reviewed, including charge collection in silicon junctions and transistors, and properties of single-event upset in CMOS static random access memory (SRAM) cells. The mechanisms are illustrated through the use of three-dimensional device and circuit simulations. Technology trends and implications for commercial devices are discussed.
The single-event upset (SEU) responses of 16 Kbit to 1 Mbit SRAMs irradiated with low and high-energy heavy ions are reported. Standard low-energy heavy ion tests appear to be sufficiently conservative for technologies down to 0.5 {micro}m.
Low-energy alpha particles emitted from packaging and high-energy heavy ions in space possess the capability of causing changes in memory state when incident on semiconductor memory cans and latch circuits. This phenomenon of single-event upset (SEU) is caused by collection of charge created as the particle travels through a sensitive volume of the device. As devices are continually down-sized, the corresponding decrease in amount of charge held on storage nodes increases device susceptibility to SEU. Solutions to harden devices to SEU require an in-depth understanding of the basic mechanisms responsible for upset. Also, a detailed understanding of the charge-collection volume is critical for predicting on-orbit error rates. Previous work has revealed the formation of a field funnel in response to the particle strike. Analytical models that treat the funnel in a time-averaged sense have been developed, and have been reasonably successful at predicting total collected charge for particles with low linear energy transfer (LET). Sophisticated two- and three-dimensional simulations have been used to investigate the funneling process more rigorously; however, the interplay between the funnel and collection by drift and diffusion has remained somewhat obscure. In this paper, we present an examination of fundamental charge-collection mechanisms and the role of the funnel, using advanced three-dimensional drift-diffusion modeling. We then apply the insight gained to address radiation hardness issues in light of current technology trends.