Publications

Two major problems associated with Si-based MEMS (MicroElectroMechanical Systems) devices are stiction and wear. Surface modifications are needed to reduce both adhesion and friction in micromechanical structures to solve these problems. In this paper, we will present a CVD (Chemical Vapor Deposition) process that selectively coats MEMS devices with tungsten and significantly enhances device durability. Tungsten CVD is used in the integrated-circuit industry, which makes this approach manufacturable. This selective deposition process results in a very conformal coating and can potentially address both stiction and wear problems confronting MEMS processing. The selective deposition of tungsten is accomplished through the silicon reduction of WF6. The self-limiting nature of the process ensures consistent process control. The tungsten is deposited after the removal of the sacrificial oxides to minimize stress and process integration problems. The tungsten coating adheres well and is hard and conducting, which enhances performance for numerous devices. Furthermore, since the deposited tungsten infiltrates under adhered silicon parts and the volume of W deposited is less than the amount of Si consumed, it appears to be possible to release adhered parts that are contacted over small areas such as dimples. The wear resistance of tungsten coated parts has been shown to be significantly improved by microengine test structures.

An overview is given on the current status of three-dimensional (3D) photonic crystals. The realization of new 3d photonic crystal structures, the creation of high Q microcavities and the building of waveguide bends are presented. These devices form the basic building blocks for applications in signal processing and low threshold lasers.

Three-dimensional photonic lattices are engineered 'materials' which are the photonic analogues of semiconductors. These structures were first proposed and demonstrated in the mid-to-late 1980's. However, due to fabrication difficulties, lattices active in the infrared are only just emerging. Wide ranges of structures and fabrication approaches have been investigated. The most promising approach for many potential applications is a diamond-like structure fabricated using silicon microprocessing techniques. This approach has enabled the fabrication of 3-D silicon photonic lattices active in the infrared. The structures display band gaps centered from 12μ down to 1.55μ.

This process combines the best features of bulk and surface micromachining. It enables the production of stress free, thick, virtually arbitrarily shaped structures with well defined, thick or thin sacrificial layers, high sacrificial layer selectivity and large undercuts using IC compatible, processes. The basis of this approach is the use of readily available {111} oriented substrates, anisotropic Si trench etching, SiN masking and KOH etching.

Silicon processing techniques were used to fabricate 3-D photonic lattices with band gaps in the infrared. The demonstration vehicle was a selective infrared mirror/band pass filter, a wide range of other applications are also possible.

Interconnect delays, arising in part from intralevel capacitance, are one of the factors limiting the performance of advanced circuits. In addition, the problem of filling the spaces between neighboring metal lines with an insulator is becoming increasingly acute as aspect ratios increase. We address these problems simultaneously by intentionally creating an air gap between closely spaced metal lines. Undesirable topography is eliminated using a spin-on dielectric. We then cap the wafers with silicon dioxide and planarize using chemical mechanical polishing. Simple modeling of test structures predicts an equivalent dielectric constant of 1.9 on features similar to those expected for 0.25 micron technologies. Two level metal test structures fabricated in a 0.5 micron CMOS technology show that the process can be readily integrated with current standard CMOS processes. The potential problems of via misalignment, overall dielectric stack height, and the relative difficulty of ensuring void formation compared to that of ensuring a void-free fill are considered.

In this work, the authors have applied mold micromachining and standard photolithographic techniques to the fabrication of parts integrated with 0.4 micron pitch diffraction gratings. In principle, the approach should be scaleable to considerably finer pitches. They have achieved this by relying on the thickness of deposited or grown films, instead of photolithography, to determine the grating pitch. The gratings can be made to extend over large areas and the entire process is compatible with batch processing. Literally thousands of parts can be batch fabricated from a single lot of six inch wafers. In the first stage of the process they fabricate a planarized silicon dioxide pad over which the silicon nitride wave guide runs. The grating is formed by first patterning and etching single crystalline silicon to form a series of trenches with well defined pitch. The silicon bounding the trenches is then thinned by thermal oxidation followed by stripping of the silicon dioxide. The trenches are filled by a combination of polysilicon depositions and thermal oxidations. Chemical mechanical polishing (CMP) is used to polish back these structures resulting in a series of alternating 2000 {angstrom} wide lines of silicon and silicon dioxide. The thickness of the lines is determined by the oxidation time and the polysilicon deposition thickness. The silicon lines are selectively recessed by anisotropic reactive ion etching, thus forming the mold for the grating. The mold is filled with low stress silicon nitride deposited by chemical vapor deposition. A wave guide is then patterned into the silicon nitride and the mold is locally removed by a combination of deep silicon trench etching and wet KOH etching. This results in a suspended diffraction grating/membrane over the KOH generated pit.

Interconnect delays, arising in part from intralevel capacitance, are one of the limiting factors in the performance of advanced integrated circuits. In addition, the problem of filling the spaces between neighboring metal lines with an insulator is becoming increasingly severe as aspect ratios increase. We address these problems by intentionally creating a air gap between closely spaced metal lines. The ends of the air gap and reentrant features are then sealed using a spin on dielectric. The entire structure is then capped with silicon dioxide and planarized . Simple modeling of mechanical test structures on silicon predicts an equivalent dielectric constant of 1.9 on features similar to those expected for 0.25 micron technologies. Metal to metal test structures fabricated in a 0.5 micron CMOS technology show that the process can be readily integrated with chemical mechanical polishing and current standard CMOS processes.

The authors have used chemical vapor deposition to grow ternary tungsten-based diffusion barriers to determine if they exhibit properties similar to those of sputter-deposited ternaries. A range of different W-B-N compositions in a band of compositions roughly between 20 and 40% W were produced. The deposition temperature was low, 350 C, and the precursors used are well accepted by the industry. Deposition rates are high for a diffusion barrier application. Resistivities range from 200 to 20,000 {micro}{Omega}-cm, the films with the best barrier properties having {approximately}1,000 {micro}{Omega}-cm resistivities. Adhesion to oxides is sufficient to allow these films to be used as the adhesion layer in a tungsten chemical mechanical polishing plug application. The films are x-ray amorphous as-deposited and have crystallization temperatures of up to 900 C. Barrier performance against Cu has been tested using diode test structures. A composition of W{sub .23}B{sub .49}N{sub .28} was able to prevent diode failure up to a 700 C, 30 minute anneal. These materials, deposited by CVD, display properties similar to those deposited by physical deposition techniques.

Bulk micromachining generally refers to processes involving wet chemical etching of structures formed out of the silicon substrate and so is limited to fairly large, crude structures. Surface micromachining allows intricate patterning of thin films of polysilicon and other materials to form essentially two-dimensional layered parts (since the thickness of the parts is limited by the thickness of the deposited films). There is a third type of micromachining in which the part is formed by filling a mold which was defined by photolithographic means. Historically micromachining molds have been formed in some sort of photopolymer, be it with x-ray lithography (``LIGA``) or more conventional UV lithography, with the aim of producing piece parts. Recently, however, several groups including ours at Sandia have independently come up with the idea of forming the mold for mechanical parts by etching into the silicon substrate itself. In Sandia`s mold process, the mold is recessed into the substrate using a deep silicon trench etch, lined with a sacrificial or etch-stop layer, and then filled with any of a number of mechanical materials. The completed structures are not ejected from the mold to be used as piece parts rather, the mold is dissolved from around selected movable segments of the parts, leaving the parts anchored to the substrate. Since the mold is recessed into the substrate, the whole micromechanical structure can be formed, planarized, and integrated with standard silicon microelectronic circuits before the release etch. In addition, unlike surface-micromachined parts, the thickness of the molded parts is limited by the depth of the trench etch (typically 10--50 {mu}m) rather than the thickness of deposited polysilicon (typically 2 {mu}m). The capability of fabricating thicker (and therefore much stiffer and more massive) parts is critical for motion-sensing structures involving large gimballed platforms, proof masses, etc.

Functioning, matrixed, field emission devices have been fabricated using a modification of standard integrated circuit fabrication techniques. The emitter-to-gate spacing is fixed by the thickness of a deposited oxide and not by photolithographic techniques. Modeling of the emitted electron trajectories using a two dimensional, Poisson solver, finite difference code indicates that much of the current runs perpendicular to plane of the part. Functioning triode structures have been fabricated using this approach. Emission current, to a collector electrically and physically separated from the matrixed array follows Fowler-Nordheim behavior.

We report on the use of a deposition/etch approach to the loss of selectivity problem, using high activity fluorine chemistries in the etch step. Proof-of-concept experiments were initially performed in a hot wall system, the excellent results obtained lead us to prove out the concept in a commercially available cold wall Genus reactor. We observed that WF{sub 6} is ineffective as an etchant of W. The technique has been able to produce perfectly selective depositions 1 micron thick in both hot wall, and cold wall, systems. Sheet resistivity values and film morphology are good. 9 refs., 4 figs., 1 tab.