Update 2: Shape anisotropy effects on magnetic domain wall dynamics in spintronic devices
Abstract not provided.
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Jump to search filtersShape anisotropy effects on magnetic domain wall dynamics in spintronic devices
Abstract not provided.
Efficient Neural Network Processing with Analog In-Memory Computing
Abstract not provided.
Device-aware inference operations in SONOS nonvolatile memory arrays
IEEE International Reliability Physics Symposium Proceedings
Non-volatile memory arrays can deploy pre-trained neural network models for edge inference. However, these systems are affected by device-level noise and retention issues. Here, we examine damage caused by these effects, introduce a mitigation strategy, and demonstrate its use in fabricated array of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) devices. On MNIST, fashion-MNIST, and CIFAR-10 tasks, our approach increases resilience to synaptic noise and drift. We also show strong performance can be realized with ADCs of 5-8 bits precision.
Evaluating complexity and resilience trade-offs in emerging memory inference machines
Abstract not provided.
Plasticity-Enhanced Domain-Wall MTJ Neural Networks for Energy-Efficient Online Learning
Abstract not provided.
Designing and Modelling Analog Neural Network Training Accelerators
Abstract not provided.
Plasticity-enhanced domain-wall MTJ neural networks for energy-efficient online learning
Proceedings - IEEE International Symposium on Circuits and Systems
Machine learning implements backpropagation via abundant training samples. We demonstrate a multi-stage learning system realized by a promising non-volatile memory device, the domain-wall magnetic tunnel junction (DW-MTJ). The system consists of unsupervised (clustering) as well as supervised sub-systems, and generalizes quickly (with few samples). We demonstrate interactions between physical properties of this device and optimal implementation of neuroscience-inspired plasticity learning rules, and highlight performance on a suite of tasks. Our energy analysis confirms the value of the approach, as the learning budget stays below 20µJ even for large tasks used typically in machine learning.
Process Variation Model and Analysis for Domain Wall-Magnetic Tunnel Junction Logic
Abstract not provided.
Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
The domain-wall (DW)-magnetic tunnel junction (MTJ) device implements universal Boolean logic in a manner that is naturally compact and cascadable. However, an evaluation of the energy efficiency of this emerging technology for standard logic applications is still lacking. In this article, we use a previously developed compact model to construct and benchmark a 32-bit adder entirely from DW-MTJ devices that communicates with DW-MTJ registers. The results of this large-scale design and simulation indicate that while the energy cost of systems driven by spin-Transfer torque (STT) DW motion is significantly higher than previously predicted, the same concept using spin-orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS subprocessor component. This result clarifies the path toward practical implementations of an all-magnetic processor system.
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