Publications

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To quantify the resolution limits of scanning microwave impedance microscopy (sMIM), we created scanning tunneling microscope (STM)-patterned donor nanostructures in silicon composed of 10 nm lines of highly conductive silicon buried under a protective top cap of silicon, and imaged them with sMIM. This dopant pattern is an ideal test of the resolution and sensitivity of the sMIM technique, as it is made with nm-resolution and offers minimal complications from topography convolution. It has been determined that typical sMIM tips can resolve lines down to ∼80 nm spacing, while resolution is independent of tip geometry as extreme tip wear does not change the resolving power, contrary to traditional scanning capacitance microscopy (SCM). Going forward, sMIM is an ideal technique for qualifying buried patterned devices, potentially allowing for quantitative post-fabrication characterization of donor structures, which may be an important tool for the study of atomic-scale transistors and state of the art quantum computation schemes.

To quantify the resolution limits of scanning microwave impedance microscopy (sMIM), we created scanning tunneling microscope (STM)-patterned donor nanostructures in silicon composed of 10 nm lines of highly conductive silicon buried under a protective top cap of silicon, and imaged them with sMIM. This dopant pattern is an ideal test of the resolution and sensitivity of the sMIM technique, as it is made with nm-resolution and offers minimal complications from topography convolution. It has been determined that typical sMIM tips can resolve lines down to ∼80 nm spacing, while resolution is independent of tip geometry as extreme tip wear does not change the resolving power, contrary to traditional scanning capacitance microscopy (SCM). Going forward, sMIM is an ideal technique for qualifying buried patterned devices, potentially allowing for quantitative post-fabrication characterization of donor structures, which may be an important tool for the study of atomic-scale transistors and state of the art quantum computation schemes.

Using scanning tunneling microscopy (STM), we investigate oxide-induced growth pits in Si thin films deposited by molecular beam epitaxy. In the transition temperature range from 2D adatom islanding to step-flow growth, systematic controlled air leaks into the growth chamber induce pits in the growth surface. We show that pits are also correlated with oxygen-contaminated flux from Si sublimation sources. From a thermodynamic standpoint, multilayer growth pits are unexpected in relaxed homoepitaxial growth, whereas oxidation is a known cause for step-pinning, roughening, and faceting on elemental surfaces, both with and without growth flux. Not surprisingly, pits are thermodynamically metastable and heal by annealing to recover a smooth periodic step arrangement. STM reveals new details about the pits' atomistic origins and growth dynamics. Here, we give a model for heterogeneous nucleation of pits by preferential adsorption of Å-sized oxide nuclei at intrinsic growth antiphase boundaries, and subsequent step pinning and bunching around the nuclei.

We describe an all-optical lithography process that can make electrical contact to nanometer-precision donor devices fabricated in silicon using scanning tunneling microscopy (STM). This is accomplished by implementing a cleaning procedure in the STM that allows the integration of metal alignment marks and ion-implanted contacts at the wafer level. Low-temperature transport measurements of a patterned device establish the viability of the process.

The digital electronics at the atomic limit (DEAL) project seeks to leverage Sandia's atomic-precision fabrication capability to realize the theorized orders-of-magnitude improvement in operating voltage for tunnel field effect transistors (TFETs) compared to CMOS. Not only are low-power digital circuits a critical element of many national security systems (e.g. satellites), TFETs can perform circuit functions inaccessible to CMOS (e.g. polymorphism).

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