This manual describes the installation and use of the Xyce™ XDM Netlist Translator. XDM simplifies the translation of netlists generated by commercial circuit simulator tools into Xyce-compatible netlists. XDM currently supports translation from PSpice, HSPICE, and Spectre netlists into Xyce™ netlists.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users' Guide. The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce. This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users' Guide.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: • Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. • A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. • Device models that are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only). • Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
This manual describes the installation and use of the Xyce™ XDM Netlist Translator. XDM simplifies the translation of netlists generated by commercial circuit simulator tools into Xyce-compatible netlists. XDM currently supports translation from PSpice, HSPICE, and Spectre netlists into Xyce™ netlists.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers; A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models; Device models that are specifically tailored to meet Sandia's needs, including some radiation-aware devices (for Sandia users only); Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase—a message passing parallel implementation—which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users' Guide. The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce. This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users' Guide.
This manual describes the installation and use of the Xyce™ XDM Netlist Translator. XDM simplifies the translation of netlists generated by commercial circuit simulator tools into Xyce-compatible netlists. XDM currently supports translation from PSpice and HSPICE netlists into Xyce™ netlists.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandias needs, including some radiation-aware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase - a message passing parallel implementation - which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users Guide. The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce. This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users Guide.
This report covers the work performed in support of the ASC Integrated Codes FY20 Milestone 7179. For the Milestone, Sandia's Xyce analog circuit simulator was enhanced to enable a loose coupling to Sandia's EIGER electromagnetic (EM) simulation tool. A device was added to Xyce that takes as its input network parameters (representing the impedance response) and short-circuit current induced in a wire or other element, as calculated by an EM simulator such as EIGER. Simulations were performed in EIGER and in Xyce (using Harmonic Balance analysis) for a variety of linear and nonlinear circuit problems, including various op amp circuits. Results of those simulations are presented and future work is also discussed.
This application note describes how Release 7.1 of the Xyce circuit simulator can be coupled with external simulators via either a Python-based interface that leverages the Python ctypes foreign function library or via the Verilog Procedural Interface (VPI). It also documents the usage of these interfaces on RHEL7 with Python 2.6 or 2.7. These interfaces are still under development and may change in the future. So, a key purpose of this application note is to solicit feedback on these interfaces from both internal Sandia Xyce users and other performers on the DARPA Posh Open Source Hardware (POSH) program.
This manual describes the installation and use of the XyceTM XDM Net list Translator. XDM simplifies the translation of netlists generated by commercial circuit simulator tools into Xyce-compatible netlists. XDM currently supports translation from PSpice and HSPICE netlists into XyceTM netlists.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: 1) Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. 2) A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. 3) Device models that are specifically tailored to meet Sandia's needs, including some radiation-aware devices (for Sandia users only). 4) Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase a message passing parallel implementation which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users' Guide. The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce. This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users' Guide.
This manual describes the installation and use of the XyCeTM XDM Net list Translator. XDM simplifies the translation of netlists generated by commercial circuit simulator tools into Xyce-compatible netlists. XDM currently supports translation from PSpice and HSPICE netlists into XyceTM netlists.
Abstract not provided.
This report summarizes the methods and algorithms that were developed on the Sandia National Laboratory LDRD project entitled "Polynomial Chaos methods in Xyce for Embedded Uncertainty Quantification in Circuit Analysis", which was project 200265 and proposal 2019-0817. As much of our work has been published in other reports and publications, this report gives a brief summary. Those who are interested in the technical details are encouraged to read the full published results and also contact the report authors for the status of follow-on projects.
This application note describes how Release 6.11 of the Xyce circuit simulator can be coupled with external simulators via either a Python-based interface that leverages the Python ctypes foreign function library or via the Verilog Procedural Interface (VPI). It also documents the usage of these interfaces on RHEL6 and RHEL7, with Python 2.6 or 2.7. These interfaces are still under development and may change in the future. So, a key purpose of this application note is to solicit feedback on these interfaces from both internal Sandia Xyce users and other performers on the DARPA Posh Open Source Hardware (POSH) program.
This application note describes some known differences in syntax, parsing, and supported features between the HSPICE and Xyce circuit simulators that might be relevant to both internal Sandia Xyce users and other performers on the DARPA Posh Open Source Hardware (POSH) program. It also presents strategies for converting HSPICE netlists and libraries to Xyce netlists and libraries.
This application note describes how the Xyce circuit simulator can be coupled with external simulators via either a Python-based interface that leverages the Python ctypes foreign function library or via the Verilog Procedural Interface (VPI). It also documents the usage of these interfaces on RHEL6 and RHEL7, with Python 2.6 or 2.7. These interfaces are still under development and may change in the future. So, a key purpose of this application note is to solicit feedback on these interfaces from both internal Sandia Xyce users and other performers on the DARPA Posh Open Source Hardware (POSH) program.
Abstract not provided.
This document is a reference guide to the Xyce Parallel Electronic Simulator, and is a companion document to the Xyce Users' Guide [1] . The focus of this document is (to the extent possible) exhaustively list device parameters, solver options, parser options, and other usage details of Xyce . This document is not intended to be a tutorial. Users who are new to circuit simulation are better served by the Xyce Users' Guide [1] . Copyright c 2002 National Technology & Engineering Solutions of Sandia, LLC (NTESS). Acknowledgements We would like to acknowledge all the code and test suite developers who have contributed to the Xyce project over the years: Alan Lundin, Arlon Waters, Ashley Meek, Bart van Bloemen Waanders, Brad Bond, Brian Fett, Christina Warrender, David Baur, David Day, David Shirley, Deborah Fixel, Derek Barnes, Eric Rankin, Erik Zeek, Gary Hennigan, Herman "Buddy" Watts, Jim Emery, Keith Santarelli, Laura Boucheron, Lawrence Musson, Mary Meinelt, Mingyu "Genie" Hsieh, Nicholas Johnson, Philip Campbell, Rebecca Arnold, Regina Schells, Richard Drake, Robert Hoekstra, Roger Pawlowski, Russell Hooper, Samuel Browne, Scott Hutchinson, Smitha Sam, Steven Verzi, Tamara Kolda, Timur Takhtaganov, and Todd Coffey. Also, thanks to Hue Lai for the original typesetting of this document in L A T E X. Trademarks Xyce Electronic Simulator TM and Xyce TM are trademarks of National Technology & Engineering Solutions of Sandia, LLC (NTESS). All other trademarks are property of their respective owners. Contact Information Outside Sandia World Wide Web http://xyce.sandia.gov Email xyce@sandia.gov Inside Sandia World Wide Web http://xyce.sandia.gov Email xyce-sandia@sandia.gov Bug Reports http://joseki-vm.sandia.gov/bugzilla http://morannon.sandia.gov/bugzilla
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been de- signed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel com- puting platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia's needs, including some radiation- aware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase -- a message passing parallel implementation -- which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
In this article, we describe a prototype cosimulation framework using Xyce, GHDL and CocoTB that can be used to analyze digital hardware designs in out-of-nominal environments. We demonstrate current software methods and inspire future work via analysis of an open-source encryption core design. Note that this article is meant as a proof-of-concept to motivate integration of general cosimulation techniques with Xyce, an open-source circuit simulator.
In this article, we describe a prototype cosimulation framework using Xyce, GHDL and CocoTB that can be used to analyze digital hardware designs in out-of-nominal environments. We demonstrate current software methods and inspire future work via analysis of an open-source encryption core design. Note that this article is meant as a proof-of-concept to motivate integration of general cosimulation techniques with Xyce, an open-source circuit simulator.