Publications

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Extended service life plastic ball grid array (PBGA) packaging with Au ball wire bonding and die-side electroless nickel electroless palladium immersion gold (ENEPIG) surface finish is in development. Post-microfabrication ENEPIG plating is proposed for the extended service life PBGA application to reduce the risk of brittle failure of wire bonds with Au-Al intermetallics over decades of exposure to thermal extremes in the field. An experimental study was undertaken to measure wire bond strength in PBGA samples with ENEPIG plating and varying die and substrate surface preparation. Liquid-phase immersion surface treatment with alkanethiol-based self-assembled monolayers (SAMs) was investigated as an alternative to argon plasma cleaning. Wire bond pull and shear force measurements per MIL-STD-883 were performed on four groups of PBGA samples with prescribed combinations of ENEPIG plating, plasma cleaning and SAM surface treatment. Results reveal that average wire bond pull and shear force in ENEPIG-plated samples exceed six grams force in all cases and are consistent with that of non-plated samples for constant bonding parameters. Surface treatment yields a measurable increase in wire bond strength relative to untreated samples, and ENEPIG-plated samples that receive plasma cleaning exhibit 23% greater average wire bond pull force relative to plated samples treated with SAMs. Wire bond strength was lower in samples where greater ENEPIG surface roughness was observed, consistent with data from the literature. The outcome supports the importance of surface cleaning for robust wire bonds, and suggests that in the context of strength, ENEPIG plating is compatible with the legacy Au ball-on-Al pad thermosonic wire bonding process. © 2012 IEEE.

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Hermetic sealing of lids in ceramic microelectronic chip carriers is typically performed with eutectic solder in relatively large belt-style reflow furnaces. This process is characterized by 30 to 45-minute cycle times at temperatures above 350 C. An experimental study was undertaken with the goal of establishing a low-cost lid sealing method marked by a compact belt furnace with lower reflow temperature and lesser cycle time. This is particularly advantageous for GaAs devices which are limited to packaging process temperatures below 300 C. A series of instrumented test samples consisting of a representative die packaged in a HTCC leadless chip carrier (LCC) was prepared. Package lids were installed and sealed in a nitrogen environment with 80-20 Au-Sn lead-free solder under various cycle time and temperature conditions. Gross and fine leak testing confirmed hermeticity. Results indicate that practical sealing can be realized in the compact furnace apparatus with measurable reductions in temperature and cycle time. Seal performance is dependent upon package orientation, which suggests the process must be calibrated for unique package designs. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy's National Nuclear Security Administration under Contract DE-AC04-94AL85000. © 2011 by ASME.

We have demonstrated a solderless flip chip bonding process that utilizes electroless nickel / palladium, immersion gold pad metallization. This mask-less process enables higher interconnect densities than can be achieved with standard solder bump reflow. The thin (100nm) immersion gold surfaces were coated with dodecanethiol self-assembled monolayers. Strong gold to gold bonds were formed at 185°C with shear strengths that exceed Mil-Std 883 requirements. Gold stud bumps are also promising for flip chip applications, and can be bonded at 150°C when the gold surfaces are properly pre-treated dilute piranha solution, argon plasma, and dodecanethiol SAM treatments work equally well. © 2011 IEEE.

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This study explores self-aligning patterns to achieve sub-micron alignment of die/wafers. We have patterned 2-d arrays of gold lines, whose width is half the periodicity, onto substrates. When commensurate patterns are brought into contact, the surface interactions between the Au lines enables high-resolution alignment, manually. Self-assembled monolayers of alkanethiols on the Au, further enhance the surface interactions, enabling alignment in less than half the time as for the uncoated die. A computation of the alignment force and torque between two featured surfaces illustrates how best to partern surfaces to maximize the tendency to align. An array of lines with a sinusoidal modulation in their spacing is more tolerant of initial misalignment, yet retains the high registration force of periodic line arrays. The optimal registration pattern might be a single spiral, as it generates both a radial force and a torque. Such patterns on die/wafers would enable precision device integration. ©The Electrochemical Society.

This study explores self-aligning patterns to achieve sub-micron alignment of die/wafers. We have patterned 2-d arrays of gold lines, whose width is half the periodicity, onto substrates. When commensurate patterns are brought into contact, the surface interactions between the Au lines enables high-resolution alignment, manually. Self-assembled monolayers of alkanethiols on the Au, further enhance the surface interactions, enabling alignment in less than half the time as for the uncoated die. A computation of the alignment force and torque between two featured surfaces illustrates how best to partern surfaces to maximize the tendency to align. An array of lines with a sinusoidal modulation in their spacing is more tolerant of initial misalignment, yet retains the high registration force of periodic line arrays. The optimal registration pattern might be a single spiral, as it generates both a radial force and a torque. Such patterns on die/wafers would enable precision device integration. ©The Electrochemical Society.

Microsystems packaging involves physically placing and electrically interconnecting a microelectronic device in a package that protects it from and interfaces it with the outside world. When the device requires a hermetic or controlled microenvironment, it is typically sealed within a cavity in the package. Sealing involves placing and attaching a lid, typically by welding, brazing, or soldering. Materials selection (e.g., the epoxy die attach), and process control (e.g., the epoxy curing temperature and time) are critical for reproducible and reliable microsystems packaging. This paper will review some hermetic and controlled microenvironment packaging at Sandia Labs, and will discuss materials, processes, and equipment used to package environmentally sensitive microelectronics (e.g., MEMS and sensors).

This late-start LDRD explores chemical strategies that will enable sub-micron alignment accuracy of dies and wafers by exploiting the interfacial energies of chemical ligands. We have micropatterned commensurate features, such as 2-d arrays of micron-sized gold lines on the die to be bonded. Each gold line is functionalized with alkanethiol ligands before the die are brought into contact. The ligand interfacial energy is minimized when the lines on the die are brought into registration, due to favorable interactions between the complementary ligand tails. After registration is achieved, standard bonding techniques are used to create precision permanent bonds. We have computed the alignment forces and torque between two surfaces patterned with arrays of lines or square pads to illustrate how best to maximize the tendency to align. We also discuss complex, aperiodic patterns such as rectilinear pad assemblies, concentric circles, and spirals that point the way towards extremely precise alignment.

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