Publications

Abstract not provided.

Electronic control systems used for quantum computing have become increasingly complex as multiple qubit technologies employ larger numbers of qubits with higher fidelity target. Whereas the control systems for different technologies share some similarities, parameters, such as pulse duration, throughput, real-time feedback, and latency requirements, vary widely depending on the qubit type. In this article, we evaluate the performance of modern system-on-chip (SoC) architectures in meeting the control demands associated with performing quantum gates on trapped-ion qubits, particularly focusing on communication within the SoC. A principal focus of this article is the data transfer latency and throughput of several high-speed on-chip mechanisms on Xilinx multiprocessor SoCs, including those that utilize direct memory access (DMA). They are measured and evaluated to determine an upper bound on the time required to reconfigure a gate parameter. Worst-case and average-case bandwidth requirements for a custom gate sequencer core are compared with the experimental results. The lowest variability, highest throughput data-transfer mechanism is DMA between the real-time processing unit (RPU) and the programmable logic, where bandwidths up to 19.2 GB/s are possible. For context, this enables the reconfiguration of qubit gates in less than 2 μs, comparable to the fastest gate time. Though this article focuses on trapped-ion control systems, the gate abstraction scheme and measured communication rates are applicable to a broad range of quantum computing technologies.

Shuttling ions at high speed and with low motional excitation is essential for realizing fast and high-fidelity algorithms in many trapped-ion-based quantum computing architectures. Achieving such performance is challenging due to the sensitivity of an ion to electric fields and the unknown and imperfect environmental and control variables that create them. Here we implement a closed-loop optimization of the voltage waveforms that control the trajectory and axial frequency of an ion during transport in order to minimize the final motional excitation. The resulting waveforms realize fast round-trip transport of a trapped ion across multiple electrodes at speeds of 0.5 electrodes per microsecond (35 m·s−1 for a one-way transport of 210 μm in 6 μs) with a maximum of 0.36 ± 0.08 mean quanta gain. This sub-quanta gain is independent of the phase of the secular motion at the distal location, obviating the need for an electric field impulse or time delay to eliminate the coherent motion.

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At Sandia National Laboratories, QSCOUT (the Quantum Scientific Computing Open User Testbed) is an ion-trap based quantum computer built for the purpose of allowing users low-level access to quantum hardware. Commands are executed on the hardware using Jaqal (Just Another Quantum Assembly Language), a programming language designed in-house to support the unique capabilities of QSCOUT. In this work, we describe a batching implementation of our custom software that speeds the experimental run-time through the reduction of communication and upload times. Reducing the code upload time during experimental runs improves system performance by mitigating the effects of drift. We demonstrate this implementation through a set of quantum chemistry experiments using a variational quantum eigensolver (VQE). While developed specifically for this testbed, this idea finds application across many similar experimental platforms that seek greater hardware control or reduced overhead.

Scalable coherent control hardware for quantum information platforms is rapidly growing in priority as their number of available qubits continues to increase. As these systems scale, more calibration steps are needed, leading to challenges with system instability as calibrated parameters drift. Moreover, the sheer amount of data required to run circuits with large depth tends to balloon, especially when implementing state-of-the-art dynamical-decoupling gates which require advanced modulation techniques. We present a control system that addresses these challenges for trapped-ion systems, through a combination of novel features that eliminate the need for manual bookkeeping, reduction in data transfer bandwidth requirements via gate compression schemes, and other automated error handling techniques. Moreover, we describe an embedded pulse compiler that applies staged optimization, including compressed intermediate representations of parsed output products, performs in-situ mutation of compressed gate data to support high-level algorithmic feedback to account for drift, and can be run entirely on chip.

Abstract not provided.