Publications

Abstract not provided.

The density of threading dislocations (TD) in GaN grown directly on flat sapphire substrates is typically greater than 10{sup 9}/cm{sup 2}. Such high dislocation densities degrade both the electronic and photonic properties of the material. The density of dislocations can be decreased by orders of magnitude using cantilever epitaxy (CE), which employs prepatterned sapphire substrates to provide reduced-dimension mesa regions for nucleation and etched trenches between them for suspended lateral growth of GaN or AlGaN. The substrate is prepatterned with narrow lines and etched to a depth that permits coalescence of laterally growing III-N nucleated on the mesa surfaces before vertical growth fills the etched trench. Low dislocation densities typical of epitaxial lateral overgrowth (ELO) are obtained in the cantilever regions and the TD density is also reduced up to 1 micrometer from the edge of the support regions.

We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.