Thermal-stress effects are shown to have a significant impact on the enhanced low-dose-rate sensitivity of linear bipolar circuits. Implications of these results on hardness assurance testing and mechanisms are discussed.
Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.
Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it is likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance.
Recent space experience has shown that the use of commercial optocouplers can be problematic in spacecraft, such as TOPEX/Poseidon, that must operate in significant radiation environments. Radiation--induced failures of these devices have been observed in space and have been further documented at similar radiation doses in the laboratory. The ubiquitous use of optocouplers in spacecraft systems for a variety of applications, such as electrical isolation, switching and power transfer, is indicative of the need for optocouplers that can withstand the space radiation environment. In addition, the distributed nature of their use implies that it is not particularly desirable to shield optocouplers for use in radiation environments. Thus, it will be important for the space community to have access to radiation hardened/tolerant optocouplers. For many microelectronic and photonic devices, it is difficult to achieve radiation hardness without sacrificing performance. However, in the case of optocouplers, one should be able to achieve both superior radiation hardness and performance for such characteristics as switching speed, current transfer ratio (CTR), minimum power usage and array power transfer, if standard light emitting diodes (LEDs), such as those in the commercial optocouplers mentioned above, are avoided, and VCSELs are employed as the emitter portion of the optocoupler. The physical configuration of VCSELs allows one to achieve parallel use of an array of devices and construct a multichannel optocoupler in the standard fashion with the emitters and detectors looking at each other. In addition, detectors similar in structure to the VCSELs can be fabricated which allows bidirectional functionality of the optocoupler. Recent discussions suggest that VCSELs will enjoy widespread applications in the telecommunications and data transfer fields.
A partially-depleted SOI transistor structure has been designed that does not require the use of specially-processed hardened buried oxides for total-dose hardness and maintains the intrinsic SEU and dose rate hardness advantages of SOI technology.
Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed.
Four general topics are covered in respect to the natural space radiation environment: (1) particles trapped by the earth`s magnetic field, (2) cosmic rays, (3) radiation environment inside a spacecraft, (4) laboratory radiation sources. The interaction of radiation with materials is described by ionization effects and displacement effects. Total-dose effects on MOS devices is discussed with respect to: measurement techniques, electron-hole yield, hole transport, oxide traps, interface traps, border traps, device properties, case studies and special concerns for commercial devices. Other device types considered for total-dose effects are SOI devices and nitrided oxide devices. Lastly, single event phenomena are discussed with respect to charge collection mechanisms and hard errors. (GHH)
A large buildup in interface traps has been observed in commercial and radiation-hardened MOS transistors at very long times after irradiation (> 10{sup 6} s). This latent buildup may have important implications for CMOS response in space. 13 refs.
Several different techniques are used to electrically characterize defects at or near the Si/SiO{sub 2} interface. Three common methods are the charge-pumping, midgap, and dual-transistor techniques. Each of these techniques offer advantages and disadvantages compared to the others. For instance, charge-pumping measurements are not significantly affected by charge lateral non-uniformities and can provide high-sensitivity measurements of the average density of interface traps. However, charge-pumping measurements cannot provide accurate measurements of the number of charged oxide traps. In contrast both the dual-tranistor and midgap techniques can provide good estimates for threshold-voltage shifts due to oxide traps and interface traps, but these estimates can break down when significant charge lateral non-uniformities are present in the oxide. Considering the widespread use of these, techniques, it is of practical and theoretical importance to quantitatively compare them. At the SISC, we will present a detailed comparison of the charge-pumping, midgap, and dual-tranistor techniques. Values for the density of interface traps measured using the three techniques will be compared for n- and P-channel transistors fabricated using several different process technologies, and under different process technologies, and under different irradiation and anneal conditions. Discrepancies between the different techniques are observed. Causes for the discrepancies will be explored at the SISC.
The effects of total-dose irradiation on PbO-ZrO{sub 2}-TiO{sub 2} ferroelectric capacitors have been studied in detail. It is shown that significant total-dose degradation of ferroelectrics can occur at dose levels greater than 1 Mrad(Si). 6 refs., 5 figs.
IEEE Transactions on Nuclear Science
The electric field dependence of radiation-induced interface- and oxide-trap charge (ΔVot and ΔVit) generation for polysilicon- and metal-gate MOS transistors is investigated at electric fields (Eox) from −4.2 MV/cm to +4.7 MV/cm. If electron-hole recombination effects are taken into account, the absolute value of ΔVot and the saturated value of ΔVit for both polysilicon- and metal-gate transistors are shown to follow an approximate E−1/2 field dependence for Eox ≥ 0.4 MV/cm. An E−1/2 dependence for the saturated value of ΔVit was also observed for negative-bias irradiation followed by a constant positive-bias anneal. This field dependence does not appear to be consistent with interface-trap formation due to hydrogen ion (H+) release in the bulk of the oxide and subsequent drift to the Si/SiO2 interface, proposed by McLean to be the likely cause of interface-trap buildup in metal-gate capacitors. The E−1/2 field dependence observed in this work suggests that the total number of interface traps created in these devices may be determined by hole trapping near the Si/SiO2 interface for positive-bias irradiation, or near the gate/SiO2 interface for negative bias irradiation, though H+ drift remains the likely rate-limiting step in the process. Based on these results, we propose a hole-trapping/hydrogen transport (HT)2 model—involving hole trapping and subsequent near-interfacial H+ release, transport, and reaction at the interface—as a possible explanation of ΔVit buildup in these polysilicon- and metal-gate transistors. © 1990 IEEE