Publications

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Ceramic packaging is crucial to the development of MEMS-based microsystems. It is an enabling technology, giving the ability to build complex packages that combine MEMS, electronics, optics, and sensors in a compact volume. In addition, ceramic hermetic packaging has a long history of providing protection to the enclosed devices, even under harsh conditions. These capabilities are being used at Sandia to package complex, MEMS-based microsystems. Looking ahead, ceramic packaging is developing new capabilities important to microsystems, such as the addition of fluidic channels. These developments will make ceramic packaging a viable option for a wide variety of compact, highly integrated microsystems. However, MEMS, particularly surface micromachines, have new reliability concerns that ceramic packaging needs to address. One example is stiction, where small amounts of water can generate surface forces large enough to cause parts to stick together. This demonstrates the need to measure and control the internal environment with greater precision than has been required in the past. Despite these challenges, it is clear that ceramic packaging will be a key technology for complex microsystems in the future.

Sandia National Laboratories has programs covering a broad range of MEMS technologies from LIGA to bulk to surface micromachining. These MEMS technologies are being considered for an equally broad range of applications, including sensors, actuators, optics, and microfluidics. As these technologies have moved from the research to the prototype product stage, packaging has been required to develop new capabilities to integrated MEMS and other technologies into functional microsystems. This paper discusses several of Sandia's MEMS packaging efforts, focusing mainly on inserting Sandia's SUMMiT™ V (5-level polysilicon) surface micromachining technology into fieldable microsystems.

Refractory ternary nitride films for diffusion barriers in microelectronics have been grown using chemical vapor deposition. Thin films of titanium-silicon-nitride, tungsten-boron-nitride, and tungsten-silicon-nitride of various compositions have been deposited on 150 mm Si wafers. The microstructure of the films are either fully amorphous for the tungsten based films, or nauocrystalline TiN in an amorphous matrix for titanium-silicon-nitride. All films exhibit step coverages suitable for use in future microelectronics generations. Selected films have been tested as diffusion barriers between copper and silicon, and generally perform extremely weH. These fiIms are promising candidates for advanced diffusion barriers for microelectronics applications. The manufacturing of silicon wafers into integrated circuits uses many different process and materials. The manufacturing process is usually divided into two parts: the front end of line (FEOL) and the back end of line (BEOL). In the FEOL the individual transistors that are the heart of an integrated circuit are made on the silicon wafer. The responsibility of the BEOL is to wire all the transistors together to make a complete circuit. The transistors are fabricated in the silicon itself. The wiring is made out of metal, currently aluminum and tungsten, insulated by silicon dioxide, see Figure 1. Unfortunately, silicon will diffuse into aluminum, causing aluminum spiking of junctions, killing transistors. Similarly, during chemical vapor deposition (CVD) of tungsten from ~fj, the reactivity of the fluorine can cause "worn-holes" in the silicon, also destroying transistors. The solution to these problems is a so-called diffusion barrier, which will allow current to pass from the transistors to the wiring, but will prevent reactions between silicon and the metal.

Structurally disordered refractory ternary films such as titanium silicon nitride (Ti-Si-N) have potential as advanced diffusion barriers in future ULSI metallization schemes. Here we present results on purely thermal metallorganic chemical vapor deposition (CVD) of Ti-Si-N. At temperatures between 300 and 450 °C, tetrakis(diethylamido)titanium (TDEAT), silane, and ammonia react to grow Ti-Si-N films with Si contents of 0-20 at.%. Typical impurity contents are 5-10 at.%H and 0.5 to 1.5 at.% C, with no O or other impurities detected in the bulk of the film. Although the film resistivity increases with increasing Si content, it remains below 1000 μΩ-cm for films with less than 5 at.% Si. These films are promising candidates for advanced diffusion barriers.

Copper chemical vapor deposition using liquid coinjection of the Cu(I) precursor (hfac)Cu(TMVS) along with TMVS has been demonstrated. The coinjection of TMVS with (hfac)Cu(TMVS) stabilizes the Cu precursor until it enters the reaction chamber, allowing for better control of the deposition and faster deposition rates. Using this technique, we have grown films with as-deposited resistivities of 1.86 {plus_minus} 0.04 {mu}{Omega}-cm, independent of film thickness. Deposition rates of well over 100 nm/min are possible. Good step coverage and gap fill down to 0.6 {mu}m lines is demonstrated, with gap fill being limited by the large Cu grain sizes in these films.